Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (30353)	9/24/1999 8:50:00 AM
From: John Walliker	Read Replies (2) \| Respond to of 93625

Carl, ...my engineering instincts say that sticking 36 800MHz transfer lines on a noisy motherboard, and then having each line go to to 25 destinations is a great way to end up with a marginal system. If you don't have enough margins, you just can't test all the possible ways that things can go wrong. Little things like some guy changing a capacitor in your power supply could cause a little extra wiggle somewhere, and your machine breaks. Firstly, what makes you think that DRDRAM uses 36 800MHz transfer lines. I only see the following Rambus signalling level high speed signals: 16/18 bit data: 16 or 18 Two differential clocks: 4 Row address: 3 Column address: 5 Total: 28 or 30 The maximum clock frequency (and the maximum frequency on any other line) is 400MHz not 800MHz. Obviously there will be harmonics present as well. As for those little wiggles from the power supply - you know perfectly well that the only capacitors that make any difference at high frequencies are those close to the devices involved. Rambus also uses a local logic reference level that travels along the route of the rest of the bus to largely cancel out any interference that might be induced in the bus wiring. I'd like to remind people that Intel had to back off on the specs of the SDRAM so much that the PC-100 spec uses parts that are typically speced to run at 125MHz, rather than just 100MHz. The difference is 25%, and that was the necessary margins. There really is no reason for the technically illiterate to believe that Intel won't have to do the same thing again, and require 1GHz RDRAMs to achieve a working 800MHz system. If you look at the design guides published on the Intel web site for PC100 modules, with the detailed requirements for matching track lengths and using defined clock distribution trees with strategically placed damping resistors and adding extra capacitors in some circumstances it is not surprising that the system specification has to be downgraded compared with the memory chips on their own. The Rambus design is not encumbered with such a messy bus interface. I could go into specifics, but it is pointless with the crowd on this thread. Why? Because we don't all agree with every point you make? Instead, they are relying on the analyses of others. But you insist we should believe only your analysis. John