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To: Process Boy who wrote (88897)	9/25/1999 1:19:00 AM
From: Amit Patel	Read Replies (2) \| Respond to of 186894

Article : Camino chipset delayed again; workaround proposed in interim (from Yahoo thread at : messages.yahoo.com Update: Camino chipset delayed again; workaround proposed in interim By Mark Hachman and Jack Robertson Electronic Buyers' News (09/24/99, 07:21:49 PM EDT) While Intel Corp. has indefinitely delayed the Camino or Intel 820 chipset due to signal integrity issues are worked out, workarounds have been proposed that could allow systems to ship. The problem, revealed Thursday night by Intel to top-tier OEMs, concerns a decline in signal integrity when a third memory slot is used in conjunction with the Camino chipset, according to Intel's customers and industry sources. A chipset redesign is likely in any event. If that is the only solution available, then the adoption of Direct Rambus DRAM will be pushed out one to three months while a new version is designed, analysts said. The question on the minds of all involved is whether a board-level fix can be implemented to allow systems to ship in the interim. More details are expected Monday, but not through an official press release from Intel. A number of workarounds have been proposed, according to industry and OEM sources. The most popular suggestion is that Intel Camino-equipped PCs could still be shipped with a cap covering the third memory slot, preventing OEMs or users from adding more memory and destroying the stability of the system. However, it was still unclear whether signal fluctuations in two-slot implementations still existed. An Intel spokesman at its Santa Clara, Calif.- headquarters declined to comment. Representatives for Rambus Inc., Mountain View, Calif., said that the problem was in a combination of the chipset, motherboard, and BIOS, but not the memory itself. “There are no known problems with the RDRAM,” said Subodh Toprani, vice-president and general manager of logic products at Rambus. Instead, the issue concerns some of the 1,000 or so permutations of three-slot Rambus boards, Toprani said. RIMMs can be populated with 4-, 6-, 8-, 10-, 12-, or 16 device configurations, each running at PC600, PC700, or PC800 speeds. Furthermore, each RIMM can use one of two connector configurations, with or without error correction code (ECC). Top-tier OEMs discovered the problems last week, sources said. Thursday night, Intel made the information generally available across the industry, advising OEMs to use two-slot memory configurations and ECC memory for the time being. In addition to the cap proposal, Intel may release stringent design guidelines that allow error-free Camino systems to ship, but in limited configurations, and without the flexibility to modify board layouts and feature sets.