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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: KM who wrote (30631)	9/25/1999 9:11:00 AM
From: Glenn Norman	Read Replies (3) \| Respond to of 93625

Yo_Ms Truff and other "BUSSERS"...................This link from the Intel thread: ebnonline.com here is a couple of quotes from the article: An Intel spokesman at its Santa Clara, Calif.- headquarters declined to comment. Representatives for Rambus Inc., Mountain View, Calif., said that the problem was in a combination of the chipset, motherboard, and BIOS, but not the memory itself. “There are no known problems with the RDRAM,” said Subodh Toprani, vice-president and general manager of logic products at Rambus. The entire article: Update: Camino chipset delayed again; workaround proposed in interim By Mark Hachman and Jack Robertson Electronic Buyers' News (09/24/99, 07:21:49 PM EDT) While Intel Corp. has indefinitely delayed the Camino or Intel 820 chipset due to signal integrity issues are worked out, workarounds have been proposed that could allow systems to ship. The problem, revealed Thursday night by Intel to top-tier OEMs, concerns a decline in signal integrity when a third memory slot is used in conjunction with the Camino chipset, according to Intel's customers and industry sources. A chipset redesign is likely in any event. If that is the only solution available, then the adoption of Direct Rambus DRAM will be pushed out one to three months while a new version is designed, analysts said. The question on the minds of all involved is whether a board-level fix can be implemented to allow systems to ship in the interim. More details are expected Monday, but not through an official press release from Intel. A number of workarounds have been proposed, according to industry and OEM sources. The most popular suggestion is that Intel Camino-equipped PCs could still be shipped with a cap covering the third memory slot, preventing OEMs or users from adding more memory and destroying the stability of the system. However, it was still unclear whether signal fluctuations in two-slot implementations still existed. An Intel spokesman at its Santa Clara, Calif.- headquarters declined to comment. Representatives for Rambus Inc., Mountain View, Calif., said that the problem was in a combination of the chipset, motherboard, and BIOS, but not the memory itself. “There are no known problems with the RDRAM,” said Subodh Toprani, vice-president and general manager of logic products at Rambus. Instead, the issue concerns some of the 1,000 or so permutations of three-slot Rambus boards, Toprani said. RIMMs can be populated with 4-, 6-, 8-, 10-, 12-, or 16 device configurations, each running at PC600, PC700, or PC800 speeds. Furthermore, each RIMM can use one of two connector configurations, with or without error correction code (ECC). Top-tier OEMs discovered the problems last week, sources said. Thursday night, Intel made the information generally available across the industry, advising OEMs to use two-slot memory configurations and ECC memory for the time being. In addition to the cap proposal, Intel may release stringent design guidelines that allow error-free Camino systems to ship, but in limited configurations, and without the flexibility to modify board layouts and feature sets. END of ARTICLE. Salude to all and to all a great "PEE WEE FOOTBALL" weekend - 'Grandpa Norman'! LONG RAMBUS for a VERY long time.

To: KM who wrote (30631)	9/25/1999 9:59:00 AM
From: capt rocky	Read Replies (1) \| Respond to of 93625

after reading 2000 posts(it seems like it) i still don't know whether the problem is with the egg or the chicken. is rmbs tech. flawed, or is intc tech flawed? for sure intc is having trouble implementing the tech into their 820 chipset.you would think after having 3 years of knowledge or rmbs tech., intc would be smart enough to know whether the damn thing worked and if they could produce it in vol. the problem may lie out of either cos. hands.not the egg or the chicken, but with the farmers. ie: the fabs. mu still hasn't announced rmbs validation. maybe the fabs. just can't build to rmbs specs in vol. the tip off there is the price and avaiability of testers. i have to think intc is not dumb . they would not continue to push rmbs if is isn't doable. the next few weeks, and statements from the horses mouths will wise us up. as i re- read this post i see all the references to the barnyard. that must be because of all the horseshit i smell. rocky. ps. the chip set will work with 2 rimms but not 3 is HORSESHIT. intc had to know.

To: KM who wrote (30631)	9/25/1999 11:36:00 AM
From: John Walliker	Read Replies (3) \| Respond to of 93625

KM, I've been reading all these engineering posts with great interest, even though I don't know a circuit board from a Ouija board. Carl has really made some compelling arguments and I would love to see some refutations if there are any. Zeev? Carl is convinced that he has proved that Rambus is a power hog compared with DDR DRAM. However, his argument was based on several starting assumptions that not everyone agrees with. 1) That Rambus will be 1 generation behind DDR because of larger die size. Therefore he compared the results from a system using 256Mbit DDR chips with 128Mbit Rambus chips. This will have biased the analysis in favour of DDR. 2) He used an obsolete Samsung data sheet for Rambus power consumption data and an advance IBM datasheet for DDR power consumption. The newer Samsung data sheet showed a significantly lower power consumption for the Intel qualified revision A silicon than the older version that Carl used. 3) The Samsung data sheet quoted maximum current consumption, while the IBM data sheet did not. When a value is not explicitly defined as being "maximum" it normally means that it is "typical", or sometimes just a guess based on a few samples. 4) Carl assumed that DDR will work reliably without bus termination. Then he revised his opinion, assuming that the clocks might need termination but not the data, address, device select and read/write lines. 5) The comparison ignored the fact that the input/output circuits of DRDRAM can be operated from a 1.8V supply while the core runs at 2.5V. This difference can reduce the power dissipation of the bus drivers by around 30% without altering the signalling voltage on the bus. 6) In applications where the memory is on the motherboard, such as games, telecommunications devices and many notebook PCs the Rambus specification allows the designer to use a much higher bus characteristic impedance than the 28 ohms specified for RIMMs. This can translate into an additional approximate halving of the Rambus signalling power consumption. Carl suggests that the Rambus designers don't know about worst-case design. A look at the design guides that can be downloaded from the Rambus web site shows quite clearly that tolerances are defined for just about everything. Carl suggests that a peak temperature of 50C might cause timing problems, while acknowledging that it is not really that high for semiconductors. The normal temperature range for commercial grade semiconductors is 0-70C. Industrial grade devices are usually rated up to 85C while military devices are rated to 125C. Some automotive parts are specified for operation up to 150C. Each Rambus chip is regularly temperature calibrated to ensure that the bus drive currrent is correct. There is an over-temperature sensor so that if the die temperature reaches a level at which the manufacturer expects the reliability to be reduced the duty cycle of the chip can be reduced, thus cooling it down. This would only happen under extreme conditions. Carl's arguments may seem compelling but they are built on foundations of sand. He devalues them by adding liberal insults and the suggestion that he alone has a clear understanding of the issues involved. John