To: Bilow who wrote (30995 ) 9/28/1999 5:44:00 AM From: Bilow Respond to of 93625
The basic problem with Rambus as an idea, is that it assumes that getting high bandwidth per pin is a great need of the electronics industry. In fact, pin counts have been exploding recently, this has decreased the need to have high bandwidth per pin. IBM is now working on standard cell packaging with 1600 pins. Rambus technology dates to the days when that was completely unexpected. In addition to the high pin count BGAs that are already on the market, new technology allowing high connectivity between chips is arising all the time. Here are some possibilities for the technology that will unseat Rambus:FormFactor to spring fine-pitch sockets on OEMs A spokesperson at Dell Computer's Personal Systems Group in Austin, Texas, confirmed that Dell had evaluated the MicroSpring approach. ... Thus, they can be used as a fine-pitch (as low as 15 mils) contact in producing array areas with thousands of contacts . techweb.com Amkor licenses LSI Logic's flip-chip technology Milpitas, Calif. - LSI Logic has given Amkor Technology Inc. access to its organic laminate flip-chip technology, which will let the IC package supplier provide high-density ball-grid array packages. Amkor (Chandler, Ariz.), will use the techniques LSI has developed to provide higher density than is possible with wire-bonded ICs. Using low-dielectric laminate substrates keeps costs down while letting I/O counts soar . LSI Logic recently tapped W.L. Gore & Associates as a supplier for laminate substrates used with flip-chip ICs. techweb.com Dense chip I/O fashioned from surface defects Xerox Palo Alto Research Center ...6,500 chip-to-package I/Os on a chip 1 centimeter square. techweb.com Will this next one be the next Rambus? I don't think so, but we do need the usual comic relief, and who knows, every now and again, something like this works:Low-cost manufacturable design offers terabit interconnects September 13, 1999,A demonstration prototype of the approach should be completed within the next six months, Jaeger said. The initial interconnect system will transmit data between chips on 100 channels at 300 Mbits /second/channel, and dissipate 1 watt of electrical power in each chip. The total bit rate will be 30 Gbits/s. techweb.com -- Carl