Hi Jim Wolf; Glad you like the catnap instructions, I'm just telling it like it is... So I went and surfed the '98 EE-Times articles for stuff on packaging, and now have a pretty good set of articles to reference.
I should mention why these are of interest to Rambus investors. Rambus is a memory technology that is designed to give high bandwidth per pin. The high bandwidth isn't the critical detail in and of itself. The critical point is that Rambus provides high bandwidth per pin. Bandwidth can also be obtained by going to wider busses, (hence the "width"). In order to properly evaluate alternatives to Rambus, we need to know how much pins cost.
So here are the reference articles. I will post replies to this post as I work out consequences and compute a few numbers, probably this week. But this is a great collection of articles, for those wanting to learn a little about the electronics industry. Note that the articles are all many months old. This is not because I want to show old information to RMBS investors, it is because the technology that is in use today, was described in articles last year (and the year before). Those articles were probably not linked to this thread, or, at least, they weren't linked in one group. So here it is, a packaging resource.
Back in March 23, 1998, EE-Times devoted an issue to packaging. It had some great articles, mostly, as is usual in EE-Times, devoted to new and future technologies:
Area-array package delivers IC benefits
cost of a die-free 208-QFP is about $1.85, while the comparable plastic-BGA-package cost is 30 percent to 50 percent higher
techweb.com
IC Packages
We're pricing at the same points as thin small outline packages, around 0.7 cents per I/O in high volumes."
techweb.com
The following article has some application to RDRAM, in that the high power consumption of the parts requires heat sinks (unlike regular memory):
Rising pin count drives material changes
The thermal output that a CSP is able to dissipate is not expected to be outside the range of 0.5 to 2 W. Greater power than this would necessitate the attachment of a heat sink
techweb.com
A great article on the future:
Array packaging: sizing up the future
In a global-array packaging price survey, Prismark found that the fully assembled cost of a film-based BGA is typically 30 percent higher than the equivalent rigid plastic one, 2 cents per ball vs. 1.5 cents per ball based on 400-I/O devices at quantities of 100,000 per month. In contrast, CSP pricing for wire-bonded film-based devices in the 100-to-200-I/O range is 1.3 cents per ball. However, the price benchmark here is SOP packaging, which comes in at 0.7 cent to 0.8 cent per lead. Tessera packages, which are also film-based, are produced in such low volume that their price is inevitably much higher, coming in at just under 3 cents per ball. The cost of these packages may fall as volume builds for such premium applications as Rambus modules, which use Tessera packaged parts today. But they may be vulnerable to lower-cost alternatives even in high-performance apps.
...
Two other factors must be considered for future array packages: the rapid reduction in the cost per bump of flip-chip and the move away from lead-frame-based cassette-handled substrates. The cost of processing a bumped wafer is continually driven and is now as low as $75 for a 150-mm wafer. It may fall below $50 per 200-mm wafer as electroless nickel and new solder application techniques come online. The number of yielded bumps per wafer is also rapidly rising as die size remains relatively constant and pin count continues its inexorable rise. The net effect of cost reduction per bumped wafer and many more bumps per wafer is fast producing an unbeatable cost per bump when compared to wire bonding. Wire bonding is mature and relatively cost inelastic. A flip-chip/wire-bond crossover price point is near at hand. The net effect is that flip-chip will proliferate.
techweb.com
Another two articles quoting pin costs on BGA packages:
VLSI improves BGA thermals March 23, 1998
Currently, package costs are "in the vicinity of plastic BGA prices, which are currently around 1.5 cents per pin," Martin said.
techweb.com
Future flip-chip technology February 02, 1998
For a small chip, the cost per bump can be less than $0.002 vs. a wirebond that currently costs $0.003 to $0.005.
techweb.com
More articles of general interest:
Foundry seeks to pioneer flip-chip in Taiwan July 20, 1998
techweb.com
Flip-chip or chip-scale? June 22, 1998
The Ultra CSP is being evaluated for memory applications, such as 48-I/O flash and 72-I/O DRAM.
techweb.com
An article showing that these new techniques are not just pie in the sky, they are going into equipment now:
IBM rolls Power 3 chip for RS/6000 October 05, 1998
The current process results in a 270 mm2 die size for the 15 million transistors. It runs on a 2.5-V supply and has five layers of metal. IBM stuck with the flip-chip technology it mastered long ago, with 1,000 interconnects on the land-grid array, 748 of which are signal pins.
techweb.com
Altera reduces lead pitch on BGA April 13, 1998
By reducing lead pitch, Altera expects to eventually pack 2,500 leads onto the same chip area that currently holds 256 balls.
techweb.com
And a pie in the sky article, for those of you who are looking for something to gamble your money away on:
Alpine hopes IC packaging achieves peak December 07, 1998
The big benefit is speed, with chip-to-chip interconnect delays below 100 picoseconds. That's because the parts are close together and messages are sent through silicon, which has a fairly low 2.65 dielectric constant.
techweb.com
-- Carl |
