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Technology Stocks : C-Cube -- Ignore unavailable to you. Want to Upgrade?

To: John Rieman who wrote (45613)	9/30/1999 9:30:00 AM
From: JEFF K	Read Replies (1) \| Respond to of 50808

John, Do you know how many chips, go into the new settop boxes(ie Sony GI SFA), and what do you figure the cost is ? The reason I ask is that Cube's purchase of TV\COM was for additional technology to incorporate into the Avia chip sets. I believe to compete with Broadcom's technology. Could there be a major product announcement coming ?

To: John Rieman who wrote (45613)	9/30/1999 11:12:00 AM
From: BillyG	Respond to of 50808

LSI Logic to rely more heavily on foundries By Peter Clarke EE Times (09/29/99, 4:23 p.m. EDT) LONDON — LSI Logic Corp. (Milpitas, Calif.) is preparing to expand its use of outsourced manufacturing. The company could outsource up to 25 percent of its manufacturing requirements within three to five years, said Bruce Entin, vice president of worldwide marketing, at a conference this week. LSI Logic first signaled a change in strategy in May when it agreed to license its G11 0.25-micron process technology to Silterra (Malaysia) Sdn. Bhd., a startup pure-play wafer fab subsidiary of Wafer Technology (Malaysia) Sdn. Bhd. funded by the Malaysian government. Entin said he expects Silterra will also license the next-generation G12 0.18-micron process technology and added, "We intend to go beyond Silterra, perhaps have several licensed fabs, and get 15 to 25 percent of manufacturing output from foundries within three to five years." Entin said the new approach will make no difference to customers. "The customer gets the same product as if it came from an LSI Logic fab. After all, it's our process," he said. Entin added that the new policy would give some customers the security of a second-source capability and provide flexibility and a useful capacity buffer for LSI Logic. Silterra's fab, located in a technology park in the northern Malaysian city of Kulim, is to be an exact copy of LSI Logic's fab in Gresham, Ore. It is expected to be running by the first quarter of 2001. Entin dismissed contentions that lower-cost manufacturing at foundries, which sometimes receive state subsidies, could eventually drive out internal manufacturing at LSI Logic. "It would take a very long time. We'll stick to a low-percentage outsourcing model for now and re-evaluate in a few years' time," he said.

To: John Rieman who wrote (45613)	9/30/1999 11:14:00 AM
From: BillyG	Respond to of 50808

Sanyo chip lets digital cameras display JPEG video By Yoshiko Hara EE Times (09/29/99, 6:05 p.m. EDT) TOKYO — To speed the ability of digital still cameras to display moving pictures, Sanyo Electric Co. has developed a system-on-chip IC that enables the VGA-resolution display of motion JPEG-compressed images. The chip is Sanyo's second to support motion JPEG. Where the first-generation IC, introduced in May, captured 10 frames/second of quarter-VGA (320 x 240-pixel) images, the new device supports 15 VGA frames/s of motion JPEG processing, or continuous shooting at a speed of 7.5 still picture frames (each with 1.5 million pixels) a second. The company said its current plans call for the IC to be used in Sanyo's own products. Sanyo has been pursuing a one-chip digital still camera (DSC) solution since 1996, said Kazuo Ito, senior manager of multimedia technology at Sanyo Multimedia. Sanyo produces dozens of different cameras, largely for the OEM market, but only a few system-on-chip ICs are needed to cover all these models. "Customers can choose which functions they plan to use, among the possibilities integrated on the device," Ito said. "To increase the number of functional blocks on a one-chip IC does not necessarily mean that the costs go up. And we can use the intellectual property for future ICs too." The company's new Super Advanced IC features a triple-bus architecture with total bandwidth of 240 Mbytes/s and consists of Sanyo's proprietary 60-MHz 32-bit embedded RISC CPU, hardwired signal-processing units and peripherals. Each of these functional units has a dedicated bus: The 32-bit signal processing bus and 16-bit peripheral bus are connected to the 32-bit CPU bus by way of bridges. Hardwired circuitry "We designed a hardwired block for pixel processing, thus avoiding burdening the CPU for [that job]," said Ito. Since the hardwired approach consumes only about one-tenth the power, he said, "The LSI consumes 800 milliwatts doing encoding and decoding of motion JPEG with hardwired circuitry." The moving VGA pictures are not obtained by cutting apart the 1.5 million-pixel image. Instead, to make use of data from all of those pixels, Sanyo developed a proprietary moving-picture processing architecture that relies on two techniques: so-called 4/8 thinning out of images, and pixel mixture. Conventional DSCs prep images for display by using two lines out of eight (2/8 thinning out). But "the picture quality is not acceptable if it is displayed in a VGA screen," said Ito. In the Sanyo scheme, the data of the upper two of every four lines is mixed with the data two lines below, then read out. In this way, data is thinned to fit VGA resolution using data from all the pixels. The IC has the capability to shoot 30 VGA frames/s, but Sanyo does not have a charge-coupled device with a doubled transfer speed yet. So its current DSC shoots only 15 frames/s. The Super Advanced IC, built in 0.35-micron three-metal-layer CMOS, integrates 3.06 million transistors or 750,000 gates in a 10.2 x 10.2-mm die. The silicon comes in a 324-pin, 18 x 18-mm BGA package. Sanyo plans to shrink the part to 0.25-micron technology soon.