To: Robert Scott Diver who wrote (5589 ) 9/30/1999 5:39:00 PM From: J R KARY Read Replies (1) | Respond to of 8218
Specs coming next week on IBM's Power4 "two-way" 1,000 mz PowerPC Right on Scott , question ML's judgement but rarely their timing . But then again , ML moving IBM lower at Opts Expir or Quarter end , with the same convoluted "non-news" , may justify questioning their timing , unless of course you believe like me that ML cares little about "day-trading" widows and orphans ;>) IBM to reveal "tape-out" specs on its new Power4 : ===== " As for IBM, the Power4 will include two CPUs connected to a large cache, making for a total of 170 million transistors, said Tony Befi, vice president of technical development at IBM's RS/6000 division, in an earlier interview. The chip is expected to run at speeds faster than 1 GHz. The two cores that will go into the Power 4 are cousins, but have differences that let them work in two types of IBM servers--the RS/6000 and AS/400 lines. By merging cores, one chip will be able to go in both types of machines. The design for the Power4 is scheduled to be complete by the end of 1999. This design milestone is known as "tape out"--when the chip blueprints are sent to a manufacturing plant that will build prototypes. IBM has built test versions of the CPU components of the Power4, each of which have 35 million transistors, Befi said. The chip should show up in servers in 2001, he said. The Power4 also will use an IBM technology called "silicon on insulator," or SOI, which enables faster chips that consume less power. It won't be the first SOI chip, though, Befi said: Updates of the Power3 and RS64-III will use SOI and run at a clock speed exceeding 500 MHz. "news.cnet.com ===== Jim K.