(COMTEX) B: HITACHI: Hitachi and STMicroelectronics unveil SH-5 micro
B: HITACHI: Hitachi and STMicroelectronics unveil SH-5 microprocessor
architecture
OCT 5, 1999, M2 Communications - Hitachi, Ltd. (TSE: 6501) and
STMicroelectronics today announced the SH-5 microprocessor
architecture, the first result of a comprehensive long-term alliance to
advance the SuperH? RISC engine family. The SH-5 64-bit architecture
provides an unparalleled combination of low price, low power
consumption and high performance for applications such as home
networking, residential gateway, digital TV, set-top box, in car
navigation and processing- intensive multimedia/video applications, as
well as high-end portable applications.
This SH-5 architecture will be presented on October 6 at the 1999
Microprocessor Forum being held in San Jose in USA.
The SH-5 architecture was developed within shared engineering
facilities in San Jose, California; ST's facility in Bristol, United
Kingdom; and Hitachi's facility in Tokyo, Japan. Sample quantities of
evaluation devices will be available in the second half of 2000 and
will be manufactured in Naka, Japan and Crolles, France. In volume,
SH-5-based products will be aggressively priced to compete in the
cost-sensitive consumer electronics market.
The SH-5's 64-bit architecture offers significant performance
advantages over the existing SH-4 family, while preserving customers'
investments in SH-4 software. New features of the SH-5 include:
extending the SuperH to 64-bit data width, developing the "SHmedia" set
of 32-bit encoded instructions for high-performance multimedia: and,
using SIMD (Single- Instruction, Multiple-Data) techniques. The
architecture also preserves the SH-4's 16-bit encoded instructions with
the "SHcompact" mode. Therefore, the SH-5 provides customers with a
clear, unfragmented migration path throughout the SuperH family. The
SHmedia instruction format includes four reserved bits, allowing for
the incorporation of additional features as the family evolves.
The upward compatibility was achieved without compromising
performance; consuming only 600mW at 400MHz/1.5V, the SH-5 delivers 714
MIPS (Millions of Instructions per Second) using Dhrystone 1.1
benchmarks and 604 MIPS using Dhrystone 2.1. For DSP-like applications,
the device provides 9.6 GOPS (Billions of Operations per Second) and
1.6 GMACS (Billions of Multiply-Accumulate operations per Second). An
optional 64-bit floating point unit can be arranged in 64x32-bit
(single-precision), 32x64-bit (double- precision) and 16x128-bit (four
single-precision) configurations, delivering 2.8 GFLOPS (Billions of
Floating Point Operations per Second) for high-end multimedia.
The SH-5 architecture has also been optimised for system-on-chip
implementations, its dual- 64-bit read/write channels, 3.2-GByte/sec
internal SuperHyway bus being augmented with two backward-compatible
peripheral buses to ensure that intellectual property (IP) blocks from
both Hitachi and STMicroelectronics will integrate with the processor
core. This will provide each of Hitachi and STMicroelectronics with a
possibility to utilise the other company's IP blocks though SuperHyway
bus and this will realise full compatibility between the manufacturers.
Both companies are currently discussing the possibility of further
developing the partnership so that a customer can approach either
Hitachi or STMicroelectronics to develop a SuperH-based SOC device and
leverage the significant IP portfolios of both companies for
system-on-a-chip designs. Additionally, since the SuperHyway bus is
compliant with the emerging VSI (Virtual Socket Interface) standard,
customers can integrate most third party IP with minimal transistors
for "wrapper" logic.
The SH-5 has been designed to meet the needs of the consumer market
and balances performance, power and price. The first CPU, specified at
400MHz, will meet these requirements and future speed enhancements to
over 600MHz give a clear performance roadmap. The first devices based
on the SH-5 architecture will be manufactured on a 0.15micron CMOS
process. The two companies will start work on the development of the
next phase of the SuperH evolution.
* SuperH(TM) is a trademark of Hitachi, Ltd.
Hitachi, Ltd., head-quartered in Tokyo, Japan, is one of the world's
leading global electronics companies, with fiscal 1998 (ended March 31,
1999) consolidated sales of 7,977 billion yen ($65.9 billion*). The
company manufactures and markets a wide range of products, including
computers, semiconductors, consumer products and power and industrial
equipment. For more information on Hitachi, Ltd., please visit
Hitachi's Web site at hitachi.co.jp.
* At an exchange rate of 121 yen to the dollar.
STMicroelectronics (formerly SGS-THOMSON Microelectronics) is a
global independent semiconductor company, whose shares are traded on
the New York Stock Exchange, on the Bourse de Paris and on the Milan
Stock Exchange. The Company designs, develops, manufactures and markets
a broad range of semiconductor integrated circuits (ICs) and discrete
devices used in a wide variety of microelectronic applications,
including telecommunications systems, computer systems, consumer
products, automotive products and industrial automation and control
systems. Further information on ST can be found at st.com.
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(C)1994-99 M2 COMMUNICATIONS LTDCONTACT: Yukiaki Ina, Hitachi, Ltd.
Tel: +81 03 3258 2055
e-mail: yina@cm.head.hitachi.co.jp
Keiko Sako, STMicroelectronics K.K
Tel: +81 03 3280 4126
e-mail: sako-st@po.iijnet.or.jp
*M2 COMMUNICATIONS DISCLAIMS ALL LIABILITY FOR
INFORMATION PROVIDED WITHIN M2 PRESSWIRE. DATA
SUPPLIED BY NAMED PARTY/PARTIES.*
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