Haim & PB - Finally - A "small" article on Intel's MDR Coppermine Presentation !
It confirms the small 106 sq. mm. die size and the cache optimizations that you and PB have been discussing.
"The new chip is defined as a Pentium III microprocessor with 256 Kbytes of on-die cache and requires 28 million transistors, or 106 sq. mm of die area. "
Paul
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Intel, Motorola share desktop-processor limelight at MPU Forum
By Mark Hachman, Electronic Buyers' News
Oct 6, 1999 (6:38 AM)
URL: ebnews.com
San Jose -- With uncertainty shrouding the fates of Centaur Technology, Rise Technology Co., and Cyrix Corp., only Intel Corp. and Motorola Inc. were left to square off with new products in the desktop portion of the Microprocessor Forum here. Intel described the technical details surrounding its new Coppermine microprocessor, while Motorola revised its PowerPC G4 microarchitecture in a bid to increase clock speeds. Normally a hotbed of technical papers, the desktop segment took a back seat to the high-end enterprise arena after Rise Technology withdrew while disclosing its entire future is up for grabs.
According to customers, Intel's Coppermine is scheduled to launch Oct. 25; the company has said only that its first products will launch at 700-MHz later this month. The new chip is defined as a Pentium III microprocessor with 256 Kbytes of on-die cache and requires 28 million transistors, or 106 sq. mm of die area. As Intel has done for some versions of the Pentium II, the chip has been designed for both mobile and desktop PCs. However, the Coppermine family will also be the first to include Intel's new Geyserville technology, which scales battery consumption down by half while maintaining 80% of the performance, the company said. Geyserville will be marketed as "SpeedStep" to OEMs.
According to Jim Wilson, product architecture manager for Intel, two areas were emphasized when the Coppermine was designed: an integrated "advanced transfer cache," and system buffering to minimize any resultant latencies.
"It's important to note that this isn't a bolt-on cache; we wanted to eliminate the inefficiencies in this particular interface," Wilson said.
The 288-bit-wide cache is 4-way set-associative, with a 32-byte line. At 700 MHz, the cache passes 11.2 Gbytes per second. In the real world, the cache will cut latency by four times compared to the latest Pentium III, he said. In other tests, the cache boosted performance 48.7% in optimized memory prefetches and 23% when used with a 3D kernel, Wilson said.
Despite the throughput improvement, analyst Keith Diefendorff of MPU Forum sponsor MicroDesign Resources, Sebastopol, Calif., noted that still, megahertz still matters.
In recognition of that fact, Motorola executives speaking at the conference said they have enhanced the PowerPC architecture to boost its frequency. Motorola referred to the new PowerPC architecture as an "enhanced G4" chip, with no product designation.
"One overall goal we had was to increase the frequency by going to a bigger pipeline, but we did not want to sacrifice performance by going to a bigger pipeline," said Naras Iyengar, senior member of the technical staff at Motorola's Somerset Design Center.
Motorola's key improvements involved lengthening the G4's pipeline from four to seven stages, while enhancing the execution units, improving the AltiVec multimedia engine, and adding a 256-Kbyte, 8-way set-associative cache.
Motorola also included two additional fixed-point units, pairing those with an existing, complex-fixed-point unit, floating-point unit, and branch execution and load/store unit. Additional instruction buffers and registers, plus a 128-entry branch target instruction cache were added, "providing additional resources for additional instructions coming through," Iyengar said. The AltiVec engine was also improved to allow two AltiVec instructions to be sent to any of the four AltiVec instruction units.
Finally, Motorola matched 32-Kbyte, 8-way set-associative instruction and data caches with a complementary 256 Kbyte level-2 cache. Although the level 2 cache can pass data in a single cycle, the penalty for a cache miss is 6 cycles. Support for up to 2 Mbytes of 64- or 128-bit off-chip level 3 cache, using either DDR or late-write SRAMs, was also included.
The chip will be designed for Motorola's 0.13-micron process technology, running over 700 MHz at 1.5 V internally. Iyengar said the revised G4 processor consumes less than 10 watts of power which the company is working to reduce even further.
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