Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Goutam who wrote (74247)	10/6/1999 12:27:00 PM
From: Elmer	Respond to of 1573230

Re: "The 288-bit-wide cache is 4-way set-associative, with a 32-byte line. " PB's post indicated it was 8-way set associative. I'm inclined to believe PB. EP

To: Goutam who wrote (74247)	10/6/1999 12:49:00 PM
From: kash johal	Respond to of 1573230

Goutama,PB and Elmer Re:"Coppermine" Well it does seem to me a very elegant approach. By getting the cache latency down I can see how this would be a huge help. So it looks like it will bring the coppermine close to parity with current Athlon performance. It will be interesting to see the performance of the Athlon with the DDR 266 memory to see if that really helps it performance. And then the MHZ ramp will be interesting. AMD folks suspect that the Athlon will be more scalable than Cumine, we'll have to wait and see. With an inferior process, they are still running ahead in MHZ. Sure will be interesting to see how the 0.18/Cu ramp goes. regards, Kash