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To: Don Lloyd who wrote (161)	10/6/1999 3:26:00 PM
From: Bilow	Read Replies (1) \| Respond to of 271

Hi Don LLoyd; Another great PDF, though more about DDR than Rambus: Note: Field Programmable Gate Arrays (FPGAs) are gate arrays that are programmed in the field, and can be reconfigured repeatedly. With the Xilinx Virtex, in fact, you can reconfigure parts of it while the rest of it is under use. They have a "macro" (i.e. a subschematic, or a subroutine) that implements a 100MHz DDR interface. The interface is 64-bits wide, so the total bandwidth is 200MHz * 8 bytes = 1.6GB/sec. This is very fast for a programmable part. Surprisingly, the description of the macro talks about Direct Rambus: Virtex Synthesizable 1.6 GBytes/s DDR SDRAM Controller While RDRAM is a revolutionary change, DDR SDRAM is a natural evolution from the existing SDRAM architecture. ... The main advantage of DDR SDRAMs over RDRAMs is the use of the system infrastructure developed for PC-100. This eliminates the numerous design changes required by different "packet" protocols. xilinx.com When you compare how simple the above circuit is compared to a RDRAM interface... -- Carl

To: Don Lloyd who wrote (161)	7/24/2000 11:37:45 AM
From: Chung Lee	Read Replies (2) \| Respond to of 271

AMD August Call/Put July 21, 2000 4PM EST AMDHL 21.88 21.62 22.12 29 217 60 AMDTL 0.00 0.50 0.69 0 487 AMDHM 17.38 17.25 17.75 93 126 65 AMDTM 1.38 1.31 1.50 95 606 AMDHN 13.50 13.38 13.88 654 1397 70 AMDTN 2.38 2.31 2.56 106 7774 AMDHO 10.00 10.12 10.62 325 1195 75 AMDTO 4.25 4.00 4.25 557 1625 AMDHP 7.50 7.38 7.75 623 3641 80 AMDTP 6.50 6.25 6.62 209 3992 AMDHQ 5.50 5.25 5.62 690 2184 85 AMDTQ 9.25 9.12 9.50 538 2191 AMDHR 3.75 3.62 3.88 855 3559 90 AMDTR 12.75 12.50 13.00 87 918 AKDHS 2.69 2.56 2.75 141 3686 95 AKDTS 14.25 16.25 16.75 42 127 AKDHT 1.75 1.69 1.88 371 3548 100 AKDTT 19.88 20.50 21.00 55 199