MY NOTES ON THE RECENT MICROPROCESSOR FORUM (PART 2):
PC Processor Evolution, Keith Diefendorff, Editor in Chief, Microprocessor Report:
ú Rapid price declines: Last year, 400 MHz was $589, now $64.
ú Frequency still rules, "especially in Celeron, where consumers are less educated." ("Less educated" were Keith's words.)
ú AMD used to trail Intel; now it's a game of leapfrog.
ú In 1998, x86 competitors gained share. Intel fought back, slashing Celeron prices. By 1Q99, Intel was the only profitable x86 vendor. Everyone underestimated Intel's willingness to fight back, and after 4Q98, Intel began regaining market share.
ú Shakeout in low-end: National and IDT gave up, sold processor divisions to Via. Rise re-evaluating its strategy, and they pulled their processor presentation out of MPF. AMD is still losing money, and Transmeta is "strangely silent."
Next-Generation Pentium III Processor with Performance Optimizations (a.k.a. Coppermine brag session), Jim Wilson, Product Architecture Manager, Intel Hillsboro:
ú 0.18u process, 6 metal layers (up from 5 with previous generations), 28 million transistors, 106 mm2 die size
ú New features: Advanced Transfer Cache (ATC) and Advanced System Buffering (ASB)
ú SpeedStep allows mobile processor to run at near desktop speeds when laptop is plugged in to a wall outlet. Frequency will automatically lower when running off of the battery to conserve power.
ú ATC: 8-way set-associative, 36-bit physical address space, >4x latency reduction, two unidirectional 288-bit back-side bus ports. "ATC is not just a bolt-on cache."
ú ATC performance benefits: 32 bytes transferred every two clocks (11.2 GB/sec @ 700 MHz), snoop stalls reduced >20x compared to today's Pentium III Xeon (Tanner), greater associativity cache gives 3% benefit for integer and 6% benefit for server apps like TPC-C.
ú ASB: Buffer sizes increased to maximize utilization of 133 MHz FSB. Fill buffers increased from 4 to 6, allowing more concurrent data cache operations. Writeback buffers increased from 1 to 4, reducing blocking during cacheline replacements. Processor can now issue up to 8 outstanding FSB transactions, an increase from 4 in the previous version.
ú Performance benefits at equal MHz are: 12% increase for SpecInt, 20% increase for SpecFP.
ú Lots of frequency headroom: "800 MHz and beyond."
ú Performance scales very well with frequency. Without ATC and ASB, performance will not have scaled as well. 800 MHz Coppermine shows 42% increase in SpecInt and 40% increase in SpecFP over 600 MHz Katmai.
Motorola's Next PowerPC Microarchitecture with AltiVec Technology, Naras Iyengar:
ú Motorola is already producing a PowerPC G4 core right now, but it's basically a G3 with AltiVec (I think).
ú Second G4 core announced in this presentation. New 7-stage pipeline (longer than before), on-chip L2 cache (256K), 64K L1 cache, support for L3 cache.
ú Clock speed of 700+ MHz, less than 10 watts power consumption, 33 million transistors, 0.13u process.
Panel: PC System Architecture Trends. Representatives from the Verdande Group (some independent organization), SiS, Intel (Jim Pappas), and Dell were there.
ú Add an additional layer of cache to the motherboard? General rule of thumb: 10:1 ratio of latency may warrant new level of cache depending on cost. However, efficiency also matters, especially when cost is a factor. Caches on the motherboard are probably dead for a while on the desktop.
ú Not enough mainstream apps that take advantage of desktop SMP, but workstations can take advantage of it. SMP could be used to fill the gap between desktop and workstation.
ú No real consensus on the amount of integration on the CPU. Cost is always a concern; however, product life cycle is also important. For example, integrating graphics does shorten the product lifetime because the AGP market moves so fast.
ú It's great to add more and more interfaces like 1394, USB, UDMA, etc. But its tough to remove old interfaces, like parallel and serial ports and ISA.
ú Rambus vs. SDRAM: There are elegant aspects of Rambus, like uniform signals and loading which were ongoing challenges in SDRAM.
ú DRAM's primary reason of being is to be cheap. This needs to be addressed first. DDR SDRAM has slight edge in cost, while the long-term depends on Rambus cost.
ú Jim of Intel said that RDRAM is the right long-term solution, while faster SDRAM will be used in the interim.
ú Over 30% of PCs are going to integrated graphics.
After this last panel discussion, there was a reception/dinner, followed by affinity sessions. I attended the one called "The Future of DRAMs: Rambus, DDR, and Beyond," but unfortunately, that session turned into a shouting match between Rambus supporters and opponents, so after asking one question, I left early.
The next day was focused on embedded processors, DSPs, and 3D graphics controllers. There was only one that I was interested in, Sun's MAJC processor, presented by its chief architect, Marc Tremblay:
ú Convergence of instruction-set architectures: VLIW (128-bit instruction packets), RISC, DSP, Java.
ú Convergence of data: Unified register file, integer, FP, fixed-point, saturated data. "Data-agnostic."
ú Convergence of I/O pipes
ú MAJC-5200 specs: 0.22u process, 500 MHz, 15 watts, 220 mm2, 6 metal layers w/ copper interconnect.
ú MAJC-5200+ specs: 0.18u process, 500 MHz @ 10 watts or 700 MHz @ 15 watts, 130 mm2, 7 metal layers w/ copper interconnect.
ú Support for graphics preprocessor. Especially useful for stuff like JTAG encoding, 2D FFT, MPEG-2 decode, AC-3 decode, etc.
ú 6.16 GFLOPs single-precision, 1.5 GFLOPs double-precision, 7 GOPS 32-bit, 13 GOPS 16-bit.
ú Space Time Computing: Two CPUs can work on different methods of a single thread. One thread is part of normal execution, while the other is being speculatively executed, with support for software rollback if there are any RAW or WAW violations.
ú Connects up to memory via RDRAM interface.
ú MAJC could be seen as combination of VLIW and thread-level parallelism.
There were other presentations that day, but I didn't pay much attention to them.
The final panel discussion was on "The Future of Microprocessor Design." Fred Pollack from Intel was there, along with people from Sun, Compaq, IBM, and AMD. Unfortunately, some of the guys on the panel turned the discussion into a Merced bash-fest.
ú Why focus on ILP with IA-64? Fred said that going to 64 bits requires a recompile anyway, so there's an opportunity to introduce a new instruction-set architecture (ISA). Intel looked at simple 64-bit extensions, RISC extensions, and EPIC. The other two extensions weren't enough, while EPIC goes beyond RISC and is better for the long term. Instead of RISC techniques like register renaming, registers will be visible to compiler.
ú AMD said that the gap between RISC and CISC is a bigger gap than RISC and EPIC. The RISC-CISC gap has already been closed, while the move to EPIC is just diminishing returns. Other benefits of EPIC are debatable. For example, predication helps eliminate branches, but branch predictors are good enough. Predication does reduce the need for out-of-order execution, but out-of-order execution is also good enough.
ú Martin Hopkins from IBM started the Merced bash-fest by calling EPIC the "longest strip-tease in history." EPIC isn't very good on clock speed. Predication lengthens the execution path. Speculation fetches unneeded data, causing I-cache problems, and it relies on infinite cache bandwidth. Based on these three factors, he felt EPIC will lose. He also accused Merced of being a machine that only looks good on the benchmarks, not on real-world apps.
ú Fred responded that there was careful attention to path length. Predication isn't done recklessly, but only where it makes sense. Pipeline length is longer than expected in Merced because of the pains of first implementations.
ú Pete Brannon of Compaq said Alpha is a "beautiful, clean architecture." It's easy to improve its performance. He called EPIC "Expect Perfectly Intuitive Compiler."
ú Fred compared the arguments against EPIC with the arguments against RISC when it was first introduced as an alternative to CISC years ago. Even though EPIC requires good compiler optimizations, so did RISC when it was introduced.
ú Sun said that customers invested billions of dollars in SPARC. Moving customers to a new ISA is very tough. Intel is trying to move toward RAS, while Sun has been doing it for years.
ú Sony's Playstation II was a very interesting topic. Sony can charge very little for the hardware and the devices and make up the profits on the software. Marty from IBM was enthusiastic over Sony's potential to dry up the revenue stream from Intel and Microsoft. (And what happens when Sony becomes the next 800 pound gorilla, Marty?)
ú In response to the PSII, Fred said the strength of the PC is the open platform. PC has momentum behind it. It triumphed not just because of Intel and Microsoft, but also because developers are all building toward the PC. When asked whether PCs will remain "in the den" and never make it to the living room, Fred said that there are lots of models of computing. Some will be satisfied by the PC, and some will not. Intel's microprocessors are a good fit for a lot of these models.
ú Marty said that game machine may be what people want. It's simple, limited capability, closed, but easy to set up and use.
That's about it for a comprehensive brain dump. Overall, it was a very informative conference for me.
Tenchusatsu |
