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To: Tenchusatsu who wrote (89735)	10/8/1999 4:54:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

More on the Coppermine foils at MPF: This is one of the foils presented at MPF regarding Coppermine's physical and electrical specifications. I'm not a process guy, but I know many people on this thread are, so I'm sure you guys will find this info very useful: 0.18u process - Decrease in minimum gate dimension for improved transistor speed - Fluorine-doped SiO2 (SiOF) dielectric for reduced capacitance resulting in global speed - Additional metal layer for routing density - Enables full-speed integrated L2 interface Design for RC - Design interconnect simulated at more than 200 MHz above target frequency - Cross-capacitance effects extensively simulated and accounted for within design - Optimized for future transistor improvement Personal note: I think that extra metal layer helped allow for the very wide L2 BSB interface as well as the increase in cache associativity from 4-way to 8-way. I'm sure other architectural improvements could have been made, maybe perhaps even a bigger L1, but I guess only the L2 was improved because it was easier to do, less risky, and better for time-to-market conditions. Tenchusatsu