Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: grok who wrote (31832)	10/8/1999 11:37:00 AM
From: Jdaasoc	Read Replies (2) \| Respond to of 93625

From Yahoo board: from Tech Data online catalog You know it's an online world. Intel's computer is linked to Tech Data computer telling them when product will ship. Do you think that Intel is going to f### up again with 840 rollout. I doubt it. We would have to be extremely stupid to get fooled again. I will praise you as a visionary if Intel fails to deliver 840 mobo by Nov 1. 10/25/99 ! I hope this is true (These ETA dates have a tendency to slip) ***** Processor: Socket Type/Chipset Intel 82801AA ICH, Intel 82802AB FWH, Intel 82840 MCH Memory: Installed Amount None Memory: Max Amount Supported 2 GB Memory: Type/Style Installed/Supported ECC Memory, RDRAM Memory: Number of Pins 168 pin Memory: Number of Sockets (4) 168 pin RIMM Memory: Speed 600 MHz, 800 MHz Memory: Must Be Added In Singles Cache: Installed Amount None Device Controller: Type Included Floppy, Ultra DMA (ATA 33/66/EIDE), Dual ChannelDevice Controller: Bus Type PCI, Integrated Device Controller: Cable Included Floppy Cable, IDE Cable Communication: Fax/Modem None Included Communication: NetworkIntegrated, Fast-Ethernet 10/100BaseTX-RJ45 Keyboard None Included Pointing Device None Included Video Card: Bus Type None Included Video Card: Features 266 MHz Data Transfer Rate Built-in Audio Features None Included Power: Voltage Requirements 3.3 VDC Ports: Serial (1) 16550 UART Ports: Parallel (1) ECP/EPP Ports: Keyboard PS/2 Style (6-Pin Mini DIN) Port Ports: Pointing Device PS/2 Style (6-Pin Mini DIN) Port Ports: Other(2) USB Bus Slot 1: Interface Type 32-bit PCI Bus Slot 1: Number Available Bus Slot 4: Interface Type(1) AGP 4X Accelerated Graphics Port (266 MHz AGP) Compliances/Certifications FCC Class B, CSA 950-95, EN 60950, IEC 950, EN 55022 Class B, EN 50082-1, UL1950 Misc FeaturesWake on LAN, Back Panel Label, Quick StartGuide, Advanced Power ManagementSupport, 1 Processor Termination Card, 2Intel P3 Processor Retention Mechanisms, 2 RDRAM Memory Continuity Cards, Board and Back Panel I/O Layout Stickers, CD-ROM S/W w/ Drivers and Product Guide *****

To: grok who wrote (31832)	10/8/1999 3:27:00 PM
From: Bilow	Respond to of 93625

Hi KZNerd; Yeah, apologies are in order. Sorry, all, for being abusive. My own experience with engineers is that they tend to scream a little at each other in the midst of technical discussions. Then when they come to a conclusion, it's all over and forgotten. If management is unfamiliar with the routine, they can get pretty weirded out. Being able to hear your best engineers, through the wall, while they are discussing design options is frequently tough on management. But the fact is that it is sometimes very hard to get someone else to understand a technical issue that may appear to be very minor to them. It turns out that shouting is a good way of getting their attention. Early on in my career I discovered that telling management how you really felt about the project was a bad idea. I tend to go through extremely quick emotions of total bliss followed by complete dread while working on a project, and it seems that a lot of other engineers do this too. The bliss comes from getting a simulation or prototype to run, while the dread comes from suddenly realizing that a calculation was in error, that I forgot to check something, or sometimes when I have made a calculation in error. Talking to management when you are in those brief complete dread periods can be really hard on them. So I don't tell them my dark calculations until they have been tested in my brain for at least a day or two. That gives me time to verify that they are real. As an example, when I first decided to use DDR, they were in the process of changing the logic levels. It became clear that the industry was standardizing on SSTL_2. At first, I ignored this, assuming that it was compatible with LVTTL_2. Then, I picked up a copy of the SSTL_2 logic description, and became convinced that I had to use VRef pins in order to get it to work. This would have blown up my pin count, so I became very, very, very worried. After about four hours of reading through the documents and calculating Vil, Voh, etc., I concluded that SSTL_2 was compatible with LVTTL_2, (which of course was the intention of the guys who designed SSTL_2). But if management had asked me what the project status was during that time, a truthful answer would have been: "I think we are dead." After years of experience, I now know to tell them instead, "I'm looking into issues regarding an interaction between the pin count and the logic levels." I guess the fact is that these engineering decisions are not trivial, and are certainly not obvious to those who don't have to make them. They are certainly not simple to those who do. -- Carl