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To: Tenchusatsu who wrote (89790)	10/10/1999 10:55:00 PM
From: Rob Young	Respond to of 186894

<21364 aka Arana aka EV8. Just discussed at MPF. Tench mentions 100% greater integer than 21264. That must be 21264 at its peak as EV8 is projected to be 200 SpecInt95 , 300 SpecFp95.> <I thought 21364 was EV7, not EV8. EV7 will integrate the RDRAM memory interface onto the chip. EV8 will introduce simultaneous multithreading. I don't recall what the schedules were, since I don't have my notes and my foils near me right now, but EV8 won't be out for quite a while.> Typo.. make that "21464 aka EV8 aka Arana". According to Alexander Wolfe who got word from Compaq folks 21364 is due to tapeout in December. Maybe not much of a stretch to see EV8 shortly after McKinley. From what I read of EV8 it doesn't require a radical reworking of the underlying architecture. Here is a link to an abstract: dec.com "The latest issue of MPF has a feature article on the Merced architecture. In the article, it says, "Intel claims a four-processor Merced system will outperform a four-way server with 1.1-GHz 21264 processors on transaction-processing benchmarks." It doesn't say who from Intel said this, and besides, it's not common practice for Intel to make such claims at this stage. But nevertheless, that claim is pretty amazing. (I don't recall hearing such a statement at the MPF conference, though.)" Well, that is easy. Probably using MSQL. Seriously, a nice target to focus on. Funny thing is that 1 GHz 21264 will be available in spades 1Q 2000 or thereabouts and if Samsung delivers according to projection, 1.5 GHz copper SOI will be the order of the day 3Q 2000. It's not that I don't believe these Intel projections, I do. Carefully crafted comparisons. I suspect that Intel will be very hard-pressed to find a benchmark Merced excels at compared to Alpha. And the machines they will have to compare against may be 21364 based machines in 3Q 2000. Reflecting on our earlier discussion of 21364... this will be an ideal server part. Low-cost servers as 21364 is described as "glue-less SMP" , i.e. the chipset is on the CPU. Yes, we ironed out where that was at, supporting circuitry for PCI busses, etc. but memory controller and network controller on-chip making for a nice box. Why shouldn't we see these 3Q 2000? But coming circular on this issue. . . if you think about it, tpmC requires great L2 bandwidth and much of it (low latency of course). So you tell me which will do better 1.5 GHz 21264 with 8 MByte of L2 at 1 GHz (nice latency there, eh?) or Merced at 700 MHz and 4 MByte L2 at 700 MHz? I acknowledge of course that the Intel person didn't know about nor could they anticipate Samsung shipping 1 GHz DDR-SRAM next year. <What do you think Marty Hopkins from IBM is going to say? It's his job to spread FUD. If EPIC isn't very accomodating to clock speeds, then what would his take be on the rumors that McKinley will have very high clock speeds? What if McKinley turns out to have higher clock speeds than IBM's own Power4?> Okay. So Marty Hopkins is offbase. Show me the error in his ways. Senior engineer/scientist like himself makes such a bold statement, maybe he is offbase in his frequency "dig". Intel certainly isn't floating up any approximations. <then what would his take be on the rumors that McKinley will have very high clock speeds? What if McKinley turns out to have higher clock speeds than IBM's own Power4?> Then he is off-base, which is possible. But of course he gets to gloat over Merced. As Fred Pollack admitted regarding Merced, the pipeline depth is a first implementation thing ... and I say "okay." "Okay" because it is a first implementation and they have to get something out the door, being a tad late and all. Rob

To: Tenchusatsu who wrote (89790)	10/10/1999 11:28:00 PM
From: Jim McMannis	Respond to of 186894

You might be interested in this...what do you think? dailynews.yahoo.com Sunday October 10 12:29 AM ET Intel Scientist Sees Chip Size, Design Limits - NYT NEW YORK (Reuters) - After 30 years of progress in the quest to make cheaper and faster computers, an Intel researcher said scientists may have reached the limit of their ability to scale down a silicon transistor crucial to the technology revolution, The New York Times reported Saturday. Citing an article in the journal Science, the Times reported that Paul Packan, a scientist with Intel Corp., the world's largest chipmaker, said semiconductor engineers have not found ways around basic physical limits beyond the generation of silicon chips that will begin to appear next year. Packan called the apparent impasse ''the most difficult challenge the semiconductor industry has ever faced.'' ''These fundamental issues have not previously limited the scaling of transistors,'' Packan wrote in the Sept. 24 issue of Science. ''There are currently no known solutions to these problems.'' For more than 30 years, the computer industry has relied on a phenomenon known as Moore's Law, named after Intel co-founder Gordon Moore, which was the basic force underlying the computer revolution and the rise of the Internet, the Times said. The law held that as transistors were scaled ever smaller -- doubling in capacity about every 18 months -- computer performance rose and the cost of computer technology dropped. It had been assumed that the progress would hold for at least another decade. Packan said the next step along Moore's Law's progression would be to develop transistors that are composed of fewer than 100 atoms -- beyond the ability of semiconductor engineers to control. Executives at Intel cautioned against seeing the problem as insurmountable, adding they were confident answers could be found. But Dennis Allison, a Silicon Valley physicist and computer designer, told the Times, ''The fact that this warning comes from Intel's process group is really significant. This says that they see actual limits.'' If the miniaturization process for silicon-based transistors is halted, hopes for continued progress would have to be based on new materials, new transistor designs and advances like molecular computing, the Times reported. Packan's report will be echoed by researchers from the University of Glasgow in a paper to be presented in December at a conference in Washington, the Times reported.