10/16 00:18 EST
IC makers take different approaches to parallelism
Oct. 15, 1999 (Electronic Buyers News - CMP via COMTEX) -- San Jose-
In a bid to enhance the performance of their microprocessors, high-end
chip designers are looking for ways to run multiple streams of
instructions at one time.
In presentations made at the recent Microprocessor Forum here, those
tactics ranged from linking together several execution units, to new
methods of managing "threads" of instructions, even to pairing more
than one microprocessor core on a single die.
In the embedded space, the concept is not new. The most recent
examples of network processors, for example, pair several smaller
application-specific processing units around a central core. But
combining several powerful microprocessor cores onto a single die as a
cheaper means of extending performance is a new design methodology, one
based on a new definition of parallelism.
Advanced Micro Devices Inc.'s x86-64 design represents an
evolutionary approach. In fact, AMD has emerged as the standard-bearer
for the x86 instruction set developed by Intel Corp. Intel's 64-bit
architecture, now called Itanium, is a new infrastructure. AMD's first
64-bit chip, named Sledgehammer, is expected to ship in 2001, company
executives said.
"The key here is that it's a simple change," said Stephen Lapinski,
director of product marketing at AMD's Computation Products Group in
Sunnyvale, Calif.
Following years of catastrophic manufacturing flubs, AMD has set out
to ensure that manufacturing the new chip will be the easiest piece of
the puzzle. Adding 64-bit capabilities increases the die size only 5%
over the approximately 104 sq. mm that a 32-bit Athlon requires, using
a 0.18-micron process, Lapinski said. While AMD's timetable still calls
for 0.18-micron manufacturing to begin at Fab 30 in Dresden, Germany,
later this quarter, the company showcased an 800-MHz Athlon running on
the new process.
More importantly, AMD claims the combination of small die size and
its 0.18-micron process will allow the company to pack more than one
64-bit x86 microprocessor on a single die. That's significant, given
the fact that x86 integer-instruction performance is closing in on RISC
chips, Lapinski said. Through IEEE-compliant, triple-operand,
double-precision floating-point instructions AMD is designing for the
new architecture, the company hopes to eliminate the floating-point
advantage of RISC chips as well, he said.
IBM Corp., Fishkill, N.Y., is one company that has embraced the
concept of single-unit multiprocessing. IBM's Power4 chip will bundle
four processing building blocks within a module that could be used
within its AS/4000 and RS/6000 servers. Within each building block, two
64-bit cores are paired, each running over 1 GHz, said Jim Kahle, chief
architect and a senior member of IBM's technical staff. Each pair of
cores shares a common Level 2 cache, which allows 100-Gbyte/s bandwidth
per block. The block can then connect via two 16-bit unidirectional
buses to off-chip Level 3 cache, providing 40 Gbytes/s. Finally, each
block can be interconnected to another processor, or attached to up to
2,200 signal I/Os or 5,500 total I/Os.
IBM's Power4, which contains 170 million transistors, is being
designed for its 0.18-micron, seven-layer metal process.
Compaq Computer Corp., by contrast, is altering the logic surrounding
its EV8 microprocessor, a chip destined for late 2002 or early 2003.
Surrounding the 1.2- to 2-GHz core will be four thread-processing units
designed to allow the chip to process more instruction threads at once
and increase the chip's performance. The basic Alpha pipeline will be
left unchanged, said Joel Emer, principal member of the technical staff
for Alpha development at Compaq, Houston.
"Alpha will maintain its single-stream performance leadership, but
simultaneous multithreading will exploit thread-level parallelism to
enhance multistream performance," Emer said.
The EV8 core will require 250 million transistors, and the chip is
expected to be manufactured in a 0.125-micron CMOS process using copper
interconnects. The superscalar processor will also feature a Direct
Rambus interface as part of a four-way system design.
---
The next parallel in processing
- AMD's 64-bit Sledgehammer sets stage for single-unit multiprocessing
- IBM's Power4 bundles eight 64-bit, 1-GHz cores
- Compaq's Alpha design wraps four thread-processing units around a
1.2- to 2-GHz EV8 core
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