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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (75796)	10/17/1999 11:18:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1572561

Re: "It seems that all you know about IC manufacturing is the defect density. " Ali... still as confused as ever. You are the one who said AMD had low yields, not me. Yields are not just related to defect density, they are a function of defect density. Here's what you said: Message 11621678 "Yes, formally it looks like "manufacturing problem" with low yields. But not because AMD transistors were weaker as you believes, but because the 4-stage design was always at huge disadvantage for manufacturability as compared to P6 counterpart." I suggest you go down to the local Junior College and ask one of the instructors what is the difference between yield and binsplit because it looks like the problem you are trying to describe is simple binsplit. So under those conditions AMD may not have had a manufacturing problem after all but simply couldn't sell all those slow parts. Don't try to make it any more complicated than that. EP

To: Ali Chen who wrote (75796)	10/18/1999 12:22:00 AM
From: THE WATSONYOUTH	Respond to of 1572561

Re: "It seems that all you know about IC manufacturing is the defect density. Too little, too superficial. Of course, for a comparable feature size process, all transistors cannot be made 100% faster than on another similar process. There must be something else to achieve that parity in CPU frequency. It is called "local optimization" at transistor level. When pushed to the limit by market demands, these "optimized" areas become very hard to manufacture. Why? Let me leave this to your imagination." I think (correct me if I'm wrong) Ali is saying that given only a 4 stage pipeline, the design could not achieve high MHz and that AMD pushed the device length too small, trying to make up for the design limitation. Maybe pushing the device length past the lower end of the design limit or past what AMD could reliably print was the cause of the low yield. IBM has somewhat similar problems with the Apple G3. It is also only a four stage pipeline design. Because of this,for good yields, it is limited to 500MHz in .25um. However, at 500MHz it is equal to 600MHz PIII in integer performance and within 10% of PIII in floating point( with an inferior floating point unit) at less than 1/3 the size and 1/5 the power. I don't consider it an inferior chip. It will be interesting to see what PPC achieves after MOTO repipelines the design. Look what Athlon achieves compared to K62/K63. THE WATSONYOUTH