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To: Glen2 who wrote (49392)	10/19/1999 2:06:00 PM
From: nolimitz	Read Replies (1) \| Respond to of 53903

OT: this could be the end for RMBS. NEC's Nintendo chip is said to be first to use DDR SDRAM By Jack Robertson Semiconductor Business News (10/19/99, 08:47:07 AM EDT) WASHINGTON -- NEC Corp.'s single graphics-memory chip for the Nintendo Corp.'s next-generation Dolphin game player will use an embedded Double Data Rate SDRAM with virtual channel -- reportedly the first DDR core to be used in the electronic game industry, according to sources. The Japanese firm Monday announced a $2.7 billion multi-year contract with Nintendo to supply the chip, which will be built on a new dedicated 0.13-micron process line co-located in NEC's Fab 8 in Kyushu (see Oct. 18 story). An NEC spokesman in Tokyo today declined to comment on any further details about the embedded DRAM chip and referred all questions to Nintendo. Sources said, however, the Double Data Rate DRAM core is necessary to achieve the 3.2-gigabytes-per-second data-transfer rate that NEC did claim for the chip. Sources also said the core will use NEC's virtual channel technique to increase the DDR speed further. NEC has asked the Joint Electron Device Engineering Council to approve a DDR spec with virtual channel. The standards body has already approved an industry standard for virtual channel with Single Data Rate SDRAM . The new 0.13-micron line, to be called No. 9, will use extended 248-nanometer krypton fluoride laser lithography, the NEC spokesman said. The firm joins a number of chip makers aiming to push 248-nm lithography to 0.13-micron feature size. The spokesman said the new production line will also use copper interconnect. NEC's Sagamihara development fab already is using copper at 0.15-micron processing in pilot production. The production line, slated to start in 2000, will have capacity of 10,000 8-inch wafers a month. The same 248-nm extended 0.13-micron design rule lithography tools are being installed in a new NEC logic fab just opened in Yamagata. That fab will be the first to use NEC's UX4 single system-on-a-chip (SOC) production system, beginning next April. NEC said the UX4 process solves one of the most perplexing production problems for SOCs: how to fabricate disparate logic and memory functions on the same chip without sacrificing performance. Usually, if production is optimized for logic, the process proves costly for memory. Conversely, if memory is optimized, logic performance might be compromised. NEC said it has been able to redesign the basic transistor structure on an SOC to optimize both the logic and memory functions. This involves changing the on current and the leakage current of the transistors in various areas of the chip. The on current and leakage current are optimized for logic functions, and different current parameters are designed for the chip's memory cores. The changes are accomplished by adding a few mask steps to the device fabrication. The first UX4 processing at 0.13-micron design rules will begin next April at Yamagata, with a capacity of 6,000 wafers a month.