all this t*ts & *ss (TA) talk has gotten me hot & bothered. how 'bout some hardcore "network processor" chat too?
sexy marketing to the rescue?
please ... ?
(several pages long so you, like me, may want to print and take this one to the can. heh heh.)
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Electronic Engineering Times
October 18, 1999, Issue: 1083
Section: Communications -- Focus: What Is A Network Processor?
Partitioning of net processors is key
Samba Murthy, Vice President of Marketing, Network Processor Group, Vitesse Semiconductor Corp., Santa Clara, Calif.
techweb.com
The recent industry standards for Gigabit Ethernet, ATM, voice-over-Internet Protocol and virtual private networks (VPNs) are creating big opportunities in the network processor chip market. The challenge for the chip supplier is to deliver innovative silicon and software solutions that meet industry standards and still provide networking OEMs with the flexibility they need to differentiate their products.
Profiting in this environment requires network hardware and software expertise, state-of-the-art chip design know-how and a compelling systems architectural vision. Enormous opportunities exist for companies that can create, utilize and retain the intellectual property required to deliver networking-chip solutions.
Most major network equipment is built using hardwired ASIC components with proprietary software. A better solution going forward would be a "user-programmable" model, where hardware and software innovations are decoupled. Typically, the deployment process for network services from prototype to large-scale deployment takes about 10 years. The slow pace is a result of the various steps: standardization, incorporation into network vendor hardware platforms, end-user procurement and installation. With the Internet Protocol, adding a new service means changing everything.
Sidgmore's Law claims that the IP traffic on the UUNet backbone is doubling every quarter during a year's time. This has a number of consequences: It means that network equipment with hundreds-of-times greater performance will be needed every three years. It also means that Internet traffic growth will force an aggressive capital investment model with operational lifetimes of less than 18 months. Moore's Law for silicon performance falls seriously short of the network needs. New, innovative equipment and chip approaches must arrive.
Internet traffic has broadened with emerging applications such as e-commerce, IP telephony and VPNs. These new applications have created a need for increased processing intelligence in the network devices to provide new services such as flow classification, access control, encryption and quality-of-service features. This requires active bandwidth management and some intelligence in the network to differentiate traffic and enable different service levels.
In the past, vertically integrated OEMs such as Cisco, 3Com, Nortel and Lucent would have tackled these tasks, defining proprietary architectures implemented by in-house ASIC engineers. However, the ever-intensifying pressure to reduce time-to-market is forcing these and other OEMs to rely more heavily on merchant semiconductor companies to carry more of the burden of circuit implementation. Chip makers that can create solutions flexible enough to allow networking OEMs to differentiate their products can be enormously successful.
A number of network processor chip products have recently been introduced to address these industry needs. Tremendous processing capacity is being delivered by this new generation of network silicon, harnessing the power of silicon integration and the application of Moore's Law to the domain of networking silicon. These products squeeze onto a single chip multiple processors, complex network functions and the promise of enormous aggregate processing capacity via parallel and distributed processing. The result is a dramatic drop in the cost of computational power applied to packet processing technology for next-generation IP networks -- 100X performance at 10X lower cost.
The new breed of network processors implement packet forwarding, classification, scheduling algorithms and multistage fabrics. The result will be a transformation from the traditional centralized router design architecture toward distributed and parallel router designs. There are subtle differences in the architecture implementation of these chips, which will result in different price, performance and scalability ratios.
An important attribute for enabling a universal network platform is programmability of the network processors. The system design must be applicable across a wide range of interfaces such as 10-, 100- and 1,000-Mbit Ethernet, FDDI, token ring, ATM, packet-over-Sonet, xDSL, multiple protocols such as IP, MPLS, VLAN, IPX, and ability to process higher protocol layers beyond Layer 3 up to Layer 7, including the data payload. The common approach taken by many of the solutions is to embed multiple RISC processors to offer parallel processing with flexibility of target application. However, this approach comes at a price-overhead needed for multicontext switching, multithread tracking and complex compilers for software development. There are also efficiency penalties associated with mismatch of the RISC engines to the "data flow" processing of network data and the ability to parallel-process "decomposed sub tasks" for performance gains.
Gigabit Ethernet network processor pioneer Xaqti, Vitesse's network processor group, takes a distinctly different approach. Xaqti is pioneering a self-synchronous, autothreaded parallel-processing architecture with the TeraPower family of Active Flow processors. A single TeraPower device can switch and route 2.5 Gbits/second of network data traffic and multiple TeraPower processors can scale to terabit-class performance. The architecture uses an assembly-line concept of parallel processing for switching and routing applications, along with multiple task-specific Active Flow processors with application-specific instruction sets. Performance scaling is achieved by employing programmability where it is needed on the assembly line.
The architecture also exploits a major industry trait-leveraging what has been invented already. The TeraPower chip can be used with off-the-shelf octal 10/100 Ethernet MACs, Gigabit Ethernet MACs, CAMs, SSRAMs and SDRAMs. Scalability is achieved with the Common Switch Interface (CSIX) to off-the-shelf fabrics from a variety of merchant silicon vendors. The open architecture and open interface allow the system designer to mix and match best-of-breed components for a truly flexible design. Product differentiation is enabled through software running on the TeraPower rather than the hardware.
The industry is slowly fostering an open marketplace for network switches. The first steps toward the availability of open published network interfaces have been taken by the CSIX Forum, founded by Xaqti, Power-X and others to promote hardware and software interoperability between network processors and fabric chips.
This will result in a market of mix-and-match interchangeable silicon components, hardware and software that enables maximum developer participation and innovation. |
