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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: John Walliker who wrote (32524)	10/21/1999 11:24:00 PM
From: Bilow	Respond to of 93625

Hi John Walliker; About that 1.5x voltage movement... This is highly confusing, but at the moment I think you are right about the 1.5x drive condition, which would be caused by two chips passing off drive without having a delay between them. Assuming perfect chips, with the master clock travelling exactly the speed of the incoming data signals, (which makes the outside chips therefore start driving proportionately earlier than the inside chips.) Lets see if I can paraphrase this, and understand it... If the first chip is outside, then its incoming trailing edge will pass through the second chip at the time that the second chip starts to drive. Therefore the second chip will see only reflections from the first chip, and no 1.5x voltages get driven. But if the first chip is inside, then the second chip would have to drive through both the (outward) reflected and the outward direct signals from the first chip. This is because the second chip has to start driving before the first chip ceases, it being farther out. This means that the second chip would have to drive the bus to 1.5x a logic 1. The above makes sense to me. I agree that some sort of state machine could keep those signals apart, but I got the impression (possibly in error) that such a state machine is not present in the standard RDRAM interface, as described on the Rambus web site. The reason I got that impression was because I noticed a table which gave the latency versus the various possible configurations. I don't recall the table including the added cycle that a miss would require. Eventually, I'll take another look at it. Their design would be much simpler if they simply increased the output compliance of the RDRAMs enough to drive a 1.5x signal. I very difficult design. When I mentioned to my engineering buddy that it seemed that Rambus was passing off reads between different chips, without dead time on the bus, he started laughing. He does more stuff outside chips than I do, so we may be misreading (or not reading) something in the spec books. It would be a lot easier to understand if they had doubly terminated that bus. I guess they didn't for at least three reasons. One was the increased power consumption, (I believe my calculations assumed a doubly terminated data bus, it is likely that my current drive calculations were in error...) The second reason was the increased number of passives required. The third was the fact that the doubly terminating some busses, but not others, would result in a system where some pins had to drive twice as much current as others. That would make it quite a bit harder to match the propagation delays. (Output pins of the controller, in particular.) New rumor of 820 not being launched Monday from Reuters. -- Carl

To: John Walliker who wrote (32524)	10/22/1999 2:26:00 AM
From: Alan Bell	Read Replies (2) \| Respond to of 93625

John, I guess I don't see where you would get a 1.5x signal. Lets look at the drivers in the memory chips, not the ones in the RAC which operate differently. The Rambus drivers are current sinks. They have no ability to source current or pull up. All the pullup current is supplied by the terminator resistor which pulls up to 1.8 v, the nominal high value. When a driver wants to assert a high, it doesn't do anything. When it wants to assert a low value, it sinks exactly enough current to pull the characteristic impedance (and terminator value) down 0.4 v to 1.4v which is the reference voltage level. This signal propagates in both directions. In the outer direction, it is absorbed by the terminator. In the inner direction, it bounces off the RAC, thereby doubling the value to 1.0v at the RAC. (Because the RAC is the only device that will examine this value, the 1.4v signal at the other RDRams data pins doesn't matter.) So the Rac will see a solid 1.0v, well below the 1.4v reference level. If two RDrams drive current should overlap slightly, the resultant incoming signal would be 1.8-0.8 until it hits the RAC which would then double it to be 1.8-1.6 or 0.2v. This is above gnd so the signal value is always between 0.2 and 1.8 thereby within the safe operating range of the Ram's and rac's input circuits. May I point you at a somewhat simplistic explanation in the pdf located at - tmo.hp.com -- Alan