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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Mani1 who wrote (76496)	10/22/1999 1:31:00 PM
From: Charles R	Read Replies (1) \| Respond to of 1574033

Excerpt from Microprocessor Watch #21 "Next year, AMD will deploy Athlon Ultra processors with up to 2M of L2 cache, which we expect to be implemented on-die. AMD is working with partner Alpha Processor (API) to develop chip sets supporting two processors on a single north bridge. AMD's new Lightning Data Transport (LDT) will connect north bridges to build systems with up to eight processors or even more. LDT will also be used to connect to I/O bridges such as PCI 64/66 and System I/O. In 2001, AMD will release SledgeHammer, a next-generation code that extends the x86 instruction set to 64 bits, much as the 386 extended the instruction set to 32 bits. SledgeHammer will also include a new floating-point instruction set (TFP) that uses RISC-like features to achieve leading-edge FP performance, as well as a few other "minor extensions." Applications that don't need 64-bit addressing or high FP performance can remain in pure x86 mode and still achieve strong performance. Combined with the high-end features already in Athlon, these new technologies will give AMD a strong base from which to launch its server initiative. AMD's challenges in the server market go far beyond technology, however. The company has no experience delivering products in a market that has been dominated by powerful processors such as SPARC, Alpha, IBM's Power, and more recently Intel's Xeon line. With Intel's Itanium (Merced) looming on the horizon, AMD will have to work hard to gain design wins in this market. But ultimately, AMD should be able to carve out a niche in the high-end market. --L.G." Like the speculation on that 2M on-die cache ;-)