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To: John Walliker who wrote (32730)	10/24/1999 8:31:00 AM
From: gnuman	Read Replies (1) \| Respond to of 93625

24/10/99 11:27am by Mike Magee theregister.co.uk

To: John Walliker who wrote (32730)	10/25/1999 1:16:00 AM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi John Walliker; This is a post largely about ground bounce (which turns out not to be something that prevents very wide memories from being implemented on a single chip). You suggested that ground bounce would be horrendous for a x64 DDR SDRAM placed in a 144-pin package. Since you are using the XCV50, a great chip, I will quote from the Xilinx document that references ground bounce, for your part: (page 9 of the Virtex Select i/O manual) Simultaneous Switching Guidelines Ground bounce can occur with high-speed digital ICs when multiple outputs change states simultaneously, causing undesired transient behavior on an output, or in the internal logic. This problem is referred to as the Simultaneous Switching Output (SSO) problem. ... Table 4 provides the guidelines for the maximum number of simultaneously switching outputs allowed per output power/ground pair to avoid the effects of ground bounce. Refer to Table 5 for the number of effective output power/ground pairs for each Virtex device and package combination. xilinx.com Table 4 includes the maximum number of simultaneously switching outputs, per power / ground pair, for various packages, and for various possible logic standards. For chip scale packages using SSTL2 Class 1, the restriction is 15. For SSTL2 Class 2, the restriction is 10. In other words, even assuming the more powerful SSTL2 Class 2, we still can switch 10 outputs per power / ground pair. Table 5 includes data for the XCV50 in the CS144 package, which is the package and part that you are designing into. The number of effective Power/Ground pairs from the table is "12". Since the package you are using provides 12 power / ground pairs, and allows simultaneous switching of at least 10 SSTL2 outputs per ground pair, this means that the maximum number of simultaneously switching outputs is 12 * 10 = 120. This is quite nearly twice the number needed for arbitrary output switching of a x64 memory chip. Now this is with an FPGA, surely a memory maker could get a full custom chip to provide resistance to ground bounce as good as that. In other words, the very FPGA you are designing with shows that ground bounce is not an issue as far as putting very wide memories into single chips. That this is true should be obvious, given the announcement of a 3.2G Byte/second memory chip to go into production in Japan. In know that this data must come as a surprise to you. Technology has a habit of creeping up on us. In other words, you turn around, and problems get solved. One of the problems that got solved was ground bounce. A big contributor to the solution is the chip scale package itself. The package reduces the pin inductance so much. Do you have another suggestion as to why x64 memories aren't feasible? As long as I'm on the same Xilinx web page, did you notice that Xilinx is providing a DDR SDRAM controller as a macrocell (programmed logic) for the Virtex series that you are using? Here is the link (of course Rambus is too difficult to hook up). xilinx.com The also have an SDRAM and a SRAM controller: xilinx.com xilinx.com -- Carl P.S. When using Xilinx, I try to look for bug fixes every day. If the investment community knew how buggy that code is they would flip. Virtex is pretty sweet in VHDL, but they don't have their schematic support (which is how you can really push the limits of the technology) up to par. In particular, the "Logiblox" support is so late, as well as the stuff that would be equivalent. (Pardon if I slip in a word that is trademarked by Altera instead of Xilinx, I frequently refer to the two company's stuff by the other company's name.)