SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Dan3 who wrote (77001)10/25/1999 11:59:00 PM
From: Cirruslvr  Read Replies (1) | Respond to of 1576822
 
Dan - RE: "DDR flat out slaughters Rambus."

Does anyone currently sell DDR SDRAM? If not, who is planning to sell it when DDR capable chipsets are available, and when will parts be available?



To: Dan3 who wrote (77001)10/26/1999
From: Cirruslvr  Respond to of 1576822
 
sorry, double post EOM.



To: Dan3 who wrote (77001)10/26/1999 1:22:00 AM
From: Tenchusatsu  Respond to of 1576822
 
Dan, <the 2.1 Gbyte/sec of DDR takes a little longer to fill a cache line than the 3.2 Gbyte/sec of dual channel rambus, but the lower latency of DDR makes up for it - should be a performance tie.>

Actually, I'm still trying to find out whether the dual Rambus channels on 840 are independent or grouped. If they're independent, then the bandwidth of a single cacheline fill is still 1.6 GB/sec, but the dual channels will allow two independent cachelines to be filled concurrently. If they're grouped, then the bandwidth of a cacheline fill is 3.2 GB/sec, although there are limitations to this setup (two RIMMs need to be populated identically, not very high bandwidth utilization, etc.)

Tenchusatsu