Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: John Walliker who wrote (77109)	10/26/1999 1:14:00 PM
From: Ali Chen	Respond to of 1577984

John, <I was hoping for something that was NOT simplified with some detailed numbers to support the assertion.> I guess the detailed numbers must be in numerous confidential white papers from RMBS to Intel. In less simplified terms it probably would take 20-25 pages of explanations and charts for various address mapping schemes. I just outlined few general ideas. "Why does the DRAM page have to be closed and then opened again at a latency of 5 to 12 bus clocks if it is momentarily not accessed. After all, Rambus is supposed to allow multiple pages to be open at once - they can't all be being accessed at the same time." I am not familiar with deep details of this particular interface, but usually there is a limit on how long you can keep a page open. The number of open pages is also limited, currently to 4 only (there was some Rambus scandal associated with this). The problem is that the write-back traffic has no resemblance with currently opened /prefetched pages, and requires a new page to be opened, with all associated full-blown latency. Closing a page in advance actually REDUCES the latency. Again, the RAMBUS protocol looks very nice in theory. Unfortunately, according to hard benchmarking facts, the reality appears to be quite a different thingy. The same story had happen with transition from EDO memory to SDRAM. Rambus just repeats the same mistake. Sorry.