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To: Tenchusatsu who wrote (33496)	11/1/1999 6:40:00 AM
From: Bilow	Respond to of 93625

Hi Tenchusatsu; Figure I'll answer for Dan, (though I may not agree with him on everything.) Re: all DDR does is increase bandwidth without changing latency. This is probably not the case. There are two reasons. The first is that most of the PC133 we've seen so far has been 3 cycle cas delayed parts. The newer PC133, as well as DDR, is likely to be only 2 cycle delayed. In addition, there are 1/2 cycle delays available on DDR, which will allow better bin splitting. The second note is that for a burst access, the arrival of the final transfer on DDR will be faster. Thus the cache line gets filled faster, which is a form of latency. That is, the latency of the full cache line is less on DDR than on PC133. (2) Re Anand's VC measurement. Dan knows a lot more about performance measurement than I ever will. No reason to embarrass myself. (3) Re die size reduction. The pin count on DDR chips is large compared to the comparable pin count on RDRAM. But modern pin technology makes this less important than it once was. Those who went to the trouble of reading my links on pin costs know that the cost of Rambus pins is about 50% higher than the cost of any other pin-out technology. This is because Rambus pins use a design that manages parasitics to a higher degree than any other pin design. In general, pin counts have always grown over the years. The original DRAM parts were in 18 pin packages, if I remember correctly, (at least the first ones I ever used were). At the time, that was considered a relatively expensive package, as most mass produced chips were in 16 pin packages. Current mainstream SDRAMs are packaged in packages that allow either 4, 8, or 16 outputs to be used. That is, the x4, x8, and x16 parts are all put into the same package. The x4 packages have 12 NCs where the x16 has I/O. Thus even in current packaging, there are more pins than are needed. Pin count problems in DRAM is almost a complete non-issue, and will become less important as time goes on. (4) It is true that RDRAM reduces the pin count of the controller. But to suggest that SDRAM requires "up-to-200" pins is a gross exaggeration. Unless power and ground pins are being counted. If power and ground pins are being counted, the number required by a Rambus channel is much higher than the number required by an SDRAM channel. This is because of the peak output current requirements of Rambus being so much larger than the peak output current requirements of SSTL_2. Pin counts on controllers has been growing through the years, just like the pin counts on DRAM have climbed. The costs per pin are around 2 cents each. New processes are coming out that allow chips with several thousand pins, for instance. Just as in the DRAM chip case, suggesting that controllers can't add pins is a simplification of a very complicated design trade off. Adding just one Rambus channel to a chip means that all the pins are likely to end up with the most technologically advanced, and therefore expensive, pins. DDR allows the use of technologies a little behind the leading edge, where costs are far lower. (5) Re Intel writing off Rambus. A more accurate statement would be that Intel is not going to write off Rambus soon. All technologies eventually become stale and are abandoned. The problem with Rambus is that it is becoming stale before it is even becoming viable. In general, the sequence of events over the last six months has been the progressive abandonment of Rambus support by Intel. They have gone from saying "no PC133", to saying, "temporary PC133, but no DDR", to saying "temporary PC133 and DDR", to saying "let the market decide". (6) At comdex, there should be some sort of working DDR machine. Maybe they'll benchmark it. Who knows? -- Carl

To: Tenchusatsu who wrote (33496)	11/1/1999 8:30:00 AM
From: Dan3	Read Replies (1) \| Respond to of 93625

Re: Shaky ground... Hi Tenchusatsu, Limited time this morning, but here's a brief response: >>>>If "it's the latency... why should DDR make any difference ...? Rambus starts off with poor latency but good bandwidth, and can't seem to improve the component latency. PCXXX transitioning to DDR starts out with good latency but poor bandwidth - DDR improves the bandwidth to better than Rambus while maintaining good latency. Best of both worlds. >>>>Anand already proved that Virtual Channel technology makes virtually no impact... Anand compared VC133 on a VIA board to PC100 on a BX board. And he ran the VC133 at CAS 3 instead of CAS 2. The BX board is typically 3% to 6% faster than VIA on most benchmarks. The VC133 more than made up that difference. It still wasn't a good test though. We need a test with PC100, PC133, and VC100, VC133 run on the same board - only NEC has done that so far, and included a whitepaper describing testing conditions that I've posted here before, and while they show a huge improvement, I don't trust their test either (I would expect them to be biased to favor their design). >>>>>DDR may be smaller in die size than RDRAM but the pin count is rather large for DDR memory chips and controllers. I think Bilow has pretty thoroughly addressed the cost of pins vs. the cost of connectors, heat sinks, etc. It seems to be a wash. Pins have gotten very cheap. >>>>>it remains to be seen whether the electricals of a 266 MHz stubby bus are easier or harder to implement than an 800 MHz continuous Rambus channel. AMD, with almost zero experience in chipset design, was able to easily implement DDR in its connection between the CPU and the chipset. Rambus has proven a nightmare to implement, even for the most experienced chipset designer on the planet. >>>Speaking of pin count, 840 demonstrates that it's relatively easy to move from a single RDRAM channel to dual channels. It still doesn't do help the inherent component latency problems of rambus. And dual channels isn't just fairly easy, it's necessary in order to provide for competitive memory expansion. And it still only provides 1 open bank for expansion. And it raises costs, both for the board and for the additional rambus heat sinks, etc. Meanwhile, DDR moves from 133/266 to 200/400 next year, with latency getting even better, costs staying just as low, and the performance advantage remaining. >>>>>Intel isn't going to write-off Rambus. Agreed, at least not for 6 months (when their PC133 and DDR chipsets are out) >>>>I still haven't seen the real benchmark results that prove DDR And I still haven't seen benchmarks of PC600 and PC700 (which will be what, 70% of the available rambus, 90%, 95%?) Compared to CAS 2 VC133. Regards, Dan PS, OK, not so brief :-)