To: pompsander who wrote (33532 ) 11/1/1999 12:12:00 PM From: unclewest Read Replies (2) | Respond to of 93625
another product designed for rmbs SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 1, 1999--Stargate Solutions Inc. (SSI), a leading supplier of semiconductor intellectual property (IP) for the networking industry, today announced its new STAR Packet and Protocol Processor core. The STAR core is a compact programmable networking processor that provides a compelling alternative to expensive network processors. The STAR (Scaleable Tile ARchitecture) Packet and Protocol Processor is based on a programmable state machine (PSM) with a simple instruction set for packet and protocol processing. The STAR approach is capable of supporting bandwidths from T1 to 2.5 Gbits/sec per port for Ethernet or Packet-Over-Sonet, and contains an instruction set optimized for multiple networking protocols such as IP-Over-Sonet, IPV4, IPV6, MPLS, ATM, and Frame Relay. With Stargate's SmartConnect feature, multiple STAR tiles can be easily connected to increase the number of ports and protocols being handled by a given piece of hardware. Since each STAR soft macro is approximately 3,500 ASIC gates, there is little die-size penalty in putting several on a single chip, making them a very cost-effective way to deliver products with a very low cost per port. A STAR tile can also be programmed to handle support for Virtual Private Network (VPN), IP tunneling, Layer 2/Layer 3 address learning, and other quality-of-service (QOS) features and functions in firmware for faster time-to-market and ease of upgrades. Future STAR products will be designed for OC192 (and higher) speeds, and for emerging protocols. The Power of Programmable State Machines STAR tiles, based on PSMs, offer the flexibility of software and the performance of hardware, and can be fine-tuned to efficiently handle multiple protocols. Each STAR contains a dynamically loadable code space that is initialized on system reset and lists specific sequences of states that personalize each particular instance of the STAR. Having several STAR tiles on a chip, with programmable firmware, increases the flexibility to change, debug, and upgrade a product anytime after the silicon is built. Complete systems can support multiple ports, variable functions, and myriad speeds using STARs, and additional ones can be connected to the internal chip bus for system redundancy. Extending the concept further, specific hardware can be added as a special block to these machines to meet high-performance requirements. For example, an interface for CAMs for longest prefix matching, IPSEC security, and interface to high-performance memory controllers like Rambus. "This approach provides a sensible, cost-effective alternative to expensive network processor chips that may not be suitable for everyone's needs," said Ram Jayam, president and CEO of Stargate. "It also gives ASIC designers unheard-of flexibility in their design approach. Engineers working with PSMs can modify their designs at any time before committing to a foundry. They can also upgrade firmware in the field. This is especially important when equipment is being optimized for standards that are still in a state of flux." The modular packaging of the STAR Packet and Protocol Processor is a valuable piece of IP for design reuse. It greatly reduces design and verification time, and can be reused with minor changes or upgrades to the firmware. Combining STAR tiles with cores from Stargate's CoreNet networking library, designers can create products for the entire range of networking solutions, from servers and switches to carrier backbones.