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To: tech101 who wrote (421)	11/2/1999 9:34:00 PM
From: tech101	Read Replies (1) \| Respond to of 1056

SOC designs may lose their allure, analyst says By Robert Ristelhueber EE Times (11/02/99, 09:59:49 AM EDT) INDIAN WELLS, Calif. ( ChipWire) -- System-on-a-chip (SOC) designs will increasingly be supplanted in coming years by multichip packaging, as higher mask costs squeeze SOC profitability, contended an analyst at the Dataquest Semiconductor conference here Monday. Chip designers have been willing to add mask steps and complexity to their devices to place analog and memory functions onto logic chips. "But when we get below 0.2-micron, we get a cost shock and the [return on investment] will be diminished or even eliminated in many cases," said Clark Fuhs, vice president and director of Dataquest's Semiconductor Manufacturing Programs. Mask costs will dramatically increase at deep submicron because of the use of phase-shift and optical proximity correction (OPC) techniques, putting low-volume SOCs at a cost disadvantage, he said. And arguing against SOC designs for many applications is the fact that there is a wide disparity in revenue-per-square-inch inside these designs, compared to having each block optimized separately, Fuhs said. "The DSP or microprocessor block can be getting $150 or $200 per square inch, the FPGA about $120, the analog block about $35, the memory block about $50 to $60," he said. "You're basically diluting your high-value logic pieces with all these other low-value pieces, yet you're adding cost because you're adding mask levels." An alternative is to fabricate the different blocks as discrete chips, placed close together using chip-scale packaging, Fuhs said. "This enables you to build the pieces in fabs that are optimized for those pieces. You can build analog in a 0.7-micron fab, standard logic can be done in 0.35- or even 0.5-micron, and for the memory you can buy a wafer from somebody and break it up. The package is more expensive, but the overall system cost is going to be substantially less. "The concept here is to take some level of interconnect . . . and simply move [it] from the chip into the package," Fuhs said, noting that Intel Corp.'s Pentium III is actually an 11-level metal device: six levels of aluminum inside the chip and five levels of copper outside the chip. Fuhs showed a photograph of a Sony Corp. digital Handycam, which he said contains 20 chip-scale devices, "so this technology is here, it's real." In the not-too-distant future, he said, wafer foundries will give customers a choice to implement a design as an SOC, or as several discrete devices using chip-scale packaging. To survive, the SOC has to evolve into more of a standard product model in order to increase volume and become more cost-efficient, Fuhs said. He predicted that within five years, multichip packaging will be growing faster than SOC designs.