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To: Tenchusatsu who wrote (33627)	11/3/1999 5:19:00 AM
From: John Walliker	Respond to of 93625

Tenchusatsu and Tony, How do they know that the "desirable" reflected signal is not reflected noise due to a mismatch The answer is that they don't. The receiver has defined upper and lower thresholds and if a signal exceeds them one way or the other coincident with a clock edge then a bit is detected. The bus specifications ensure that those small reflections that will inevitably occur are well below the receive threshold. The fact that reflection is used to double the signal level is irrelevant, because it applies equally to wanted and unwanted signals being received at the controller. It is just a neat way of saving power. If you think about a lightly terminated bus such as is used in SDRAM, reflections also take place at both ends and at any stubs such as pcb tracks within DIMMs and it is only when those reflections have settled down that the bus voltage becomes stable. Technologies such as SSTL2 have evolved to mitigate some of the effects of such ringing by catching the first overshoot and holding its logic level. John