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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Saturn V who wrote (92463)	11/15/1999 1:30:00 AM
From: THE WATSONYOUTH	Read Replies (1) \| Respond to of 186894

Re: "I thought of the same thing.But there is a problem with the scenario.The standard isotropic etch WILL NOT lead to the notched structure in the published picture.The poly will etch laterally from the place the isotropic etch is begun.The notch will be in the wrong place,ie the middle of the poly as opposed to the bottom, near the source drain. So I am still puzzled. The poly etch rate has to increase as the gate oxide is approached. I am still speculating how that can be done. Control the doping profile of the poly and use a isotropic etch, whose etch rate is a function of doping density ?" I see your point. However, isotropic etch processes can have etch rates that are very load dependent. By this I mean that when the isotropic process is first started, the global poly pattern factor is probably around 70% (70% of the wafer is being etched while 30% are gates)) Under these conditions, the lateral etch component can be quite small. As the poly clears down to gate oxide, the local poly pattern factor rapidly goes down (only the sidewalls are now exposed) With this much reduced poly load, the lateral etch component speeds up considerably. Most of the notching may occur only during the overetch (after the poly clears off the field) If so, this would necessitate the dummy gates to equalize the resulting load even on a local basis. However, I doubt Intel predopes the gates (implanted before etching) as you speculated. I don't pretend to know exactly how they do this. I doubt they predicted this profile themselves. Probably entirely empirical. Usually that's the way it works. The theories come later. THE WATSONYOUTH