Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Process Boy who wrote (92659)	11/17/1999 2:21:00 AM
From: Gary Ng	Read Replies (2) \| Respond to of 186894

PB, Re: Sincere congratulations to the Coppermine design teams. :-). From the spec score, it seems that i840 with RDRAM really don't show too much performance gain comparing to 440BX. Just curious what would be the typical application mix where one can see the real benefit of i840/RDRAM. Gary

To: Process Boy who wrote (92659)	11/17/1999 5:43:00 AM
From: Haim Barad	Read Replies (1) \| Respond to of 186894

Sincere congratulations to the Coppermine design teams. :-). PB Don't forget the compiler team as well. (although getting performance via SW is not legit according to some who visit this thread) Haim

To: Process Boy who wrote (92659)	11/17/1999 9:27:00 PM
From: Dan3	Respond to of 186894

Re: congratulations to the Coppermine design teams.... There may be (at least partly) some other things going on. Most standard benchmarks show a lot less improvement than those run with the new prefetch compiler - but that may be important good news for Intel. Could it be that we are seeing a first example of some of the compiler technology that has been under development for merced(itanium)? I've always been a little skeptical of the VLIW approach, since modern compilers have to be oriented more and more to multithreading for multiprocessors, and I conjecture (perhaps wrongly)that optimizations for multithreading would interfere with VLIW optimizations. It also seemed that developing an effective compiler for VLIW might not even be possible. These new spec results, however, show the new prefetch compiler to be very effective at scheduling instructions and data loads to optimize processor performance with the new L2 cache, and that may bode well for a compiler that will be able to create executables that will get good performance from the IA-64 architecture. If it can keep that L2 fully occupied, maybe a variation can keep all of the IA-64 registers and logic units busy. (or maybe there's just a lot of hand-coded assembler that's specific to SPEC95, and it's all smoke and mirrors - but those numbers look darn good) Dan