To: Proud_Infidel who wrote (33309 ) 11/22/1999 12:36:00 PM From: Proud_Infidel Read Replies (3) | Respond to of 70976
Speaking of change: 1999 roadmap accelerates MPU technology, cites need for paradigm shift in 15 years By J. Robert Lineback Semiconductor Business News (11/22/99, 12:16:07 PM EDT) SAN JOSE -- The Semiconductor Industry Association today previewed the awaited 1999 edition of the International Technology Roadmap for Semiconductors, which breaks out a new class of products--called "performance system on-a-chip"--and suggests that scaling of conventional CMOS transistors may no longer be possible 15 years from now. The roadmap is the first SIA-sponsored document to be jointly produced with trade groups from Europe, Japan, South Korea, and Taiwan. Trade groups from these regions provided input to the 1998 update of the SIA National Technology Roadmap for Semiconductors last year. Following months of debate about the pace of the 1999 roadmap, technical committees and organizers decided to use a three-year cycle for technology nodes and four basic IC groups to plot targeted device shrinks. DRAM pitch length matches up with the technology nodes, while microprocessor gate lengths are smaller than the feature sizes in the nodes. The 1999 roadmap tables also track MPU/ASIC pitch and ASIC gate lengths. The new roadmap leaves the 0.13-micron technology node at 2002--as is the case in the 1998 update, which was released earlier this year. DRAM pitch is also still set at 0.13-micron in 2002, while microprocessor gate-length shrinks were accelerated in the new document from the 1998 update. The 1999 roadmap shows MPU gate lengths being at 0.090-0.085 micron in 2002 vs. 0.10 micron as shown in the the 1998 update. The 1999 roadmap targets are a compromise between groups wanting to accelerate the pace of microprocessor technology and DRAM makers--primarily in Asia--wanting to stay with the traditional three-year technology pace (see June story on the debate). The technology nodes and product targets indicated when the roadmap committees believe a level of process technology will be introduced into volume production. The 100-nanometer (0.10-micron) node is set for 2005 (with DRAM pitch targets being 0.10 micron and MPU gate lengths at 0.065 micron. The new global semiconductor roadmap sets the 70-nm technology node in 2008 (DRAM pitch at 0.07 micron and MPU gates at 0.045 micron). The 50-nm node is expected to arrive in 2011 with DRAM pitch being at 0.05 micron and microprocessor gate lengths at 0.032-0.-32 micron. When the 35-nm technology arrives in 2014, DRAM pitch will be at 0.035 micron and MPU gates will be down to 0.022-0.020 micron, according to the 1999 roadmap. It is at that point that the international roadmap says conventional CMOS scaling may hit the end of the road. "It is difficult for most people in the semiconductor industry to imagine how we could continue to afford the historic trends of increase in process equipment and factory costs for another 15 years!" said the 1999 roadmap, referring to some projections of wafer fabs that could cost as much as $10 billion (see feature story from July issue of SBN magazine). "Thus, future editions of the ITRS [International Technology Roadmap for Semiconductors] may begin pointing toward more radical approaches to perpetuate our ability to further reduce the cost-per-function and increase the performance or integrated circuits. "It is probable that such approaches will involve new devices as well as new manufacturing paradigms," said the new roadmap.