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To: John Walliker who wrote (35018)11/23/1999 12:46:00 PM
From: Bilow  Respond to of 93625
 
Hi John Walliker; Re bank control for RDRAM on the 820 chipset:

The Intel 820 chipset implements power management by assigning DRDRAMs to either "pool A" or "pool B". A-pool devices are in either ACTIVE or STANDBY mode, while "B" pool devices are normally in NAP mode. Hardware configuration registers are used to set the size of the A-pool to either 1, 2, 4, or 8 devices and also set the maximum number of ACTIVE devices in the A-pool to 1, 2, or 4 devices. The 820 supports a maximum of 8 open pages across all DRDRAMs in the system. The 820 can be set to optionally monitor inactivity on the Rambus channel, and if a threshold is exceeded then the least recently used (LRU) device in the A-pool is demoted to the B-pool. If an access is made to a B-pool device, it will need to become ACTIVE and an existing A-pool device may have be demoted to the B-pool to satisfy the active device limit.

As an additional protection against RIMM overheating, the 820 can be set to throttle memory activity based on either continuous checking of the time averaged memory traffic levels or by monitoring the thermal trip sensor in each DRDRAM. This monitoring is performed on a polling basis when the 820 performs an I/O current calibration on each memory device every 100 ms. When throttling is invoked the chipset halts memory accesses once the number performed within the current throttling interval exceed a programmed threshold.

realworldtech.com

-- Carl