SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Cirruslvr who wrote (80999)11/24/1999 4:11:00 PM
From: Tenchusatsu  Read Replies (1) | Respond to of 1574102
 
Cirrus, another thing to consider about AMD's release schedule for Mustang is that they might not have any 4-way chipsets to support it. A two-way system might have up to 1M of L2 cache on each processor, but going to 2M is clearly overkill. So I'm not very sure that a 2M Mustang is necessary until the 4-way chipsets are released. Maybe 1M Mustang.

By the way, some people might think that the point-to-point bus allows AMD to get away with smaller L2 caches. This is incorrect, because no matter how you slice it, cache misses are still bad, whether it's on a shared MP bus or multiple P2P ports.

<Does anyone know if there any way using copper can enhance yields on processors with on-chip cache? Or is it speed related only?>

I think the copper interconnect is a speed and power thing. Yields could even be somewhat worse, depending on how mature AMD's copper process is by the time Mustang is released.

Tenchusatsu