To: Process Boy who wrote (81378 ) 11/29/1999 8:29:00 PM From: Dan3 Respond to of 1572563
Re: From what I know about it, the scenario you are putting out there would virtually be an impossibility.... Hi PB, Could be. I am no "expert in the field" on this one. But there are companies whose inventory consists of "IP" (intellectual property). Here's an article that agrees with you, at least in the context of two companies (say, NEC and Motorola) having problems componentizing portions of large systems such as SoC: ===================================================== Both the Virtual Socket Interface Alliance (VSIA) and the Reuse Methodology Manual (RMM) come up short. VSIA should be commended for its vision, but its Virtual Component Interface addresses only data-flow issues. It ignores sideband control signaling and manufacturing test issues necessary for a standardized IP core interface to enable efficient SoC integration, debug and test strategies. The RMM, written by designers at Synopsys and Mentor Graphics, documents good design practices for making core reuse controllable, predictable and repeatable. Unfortunately, it is only text. Implementation remains an exercise for the VLSI designer. To fix the design-reuse problem, the industry needs a complete IP-core interface standard comprising data, control and test. Such a standard would allow cores to be independently created, integrated and tested as true system "components" decoupled from the SoC interconnect. Until such a standard is publicly available, SoC design will not proliferate to the mainstream.eetimes.com ===================================================== But I tend to think that Intel sharing with Intel might go a little easier. Continuing on: ======================================================== "Taiwan is at a historical turning point," added Macronix's Yiu. "Do the foundries become IP integrators, or stay behind and be integrated themselves?" Neither executive offered specific suggestions on Taiwan's foundries could boost their IP capabilities. But Yiu projected that customers will increasingly go only to foundries that can manage the complex integration of widely disparate IP cores and processes to produce SOC devices.. eetimes.com ========================================================= Seems to indicate that division of labor and reuse of IP in large, complex design projects is being considered as a way to foster development. Since L2 cache is still most often found as an entirely separate component (as on earlier PIIIs, Athlon, etc.) It should be a good candidate for this kind of IP sharing. I'm not so sure that it is quite as unbelievable as you imply for some of the "IP" developed by the willamette/foster team to be shared with the coppermine team. but I could be completely wrong - and I doubt the details of coppermine's development will be released until it's no longer considered to be information that could be helpful to competitors. Regards, Dan