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To: Proud_Infidel who wrote (33425)12/4/1999 10:40:00 AM
From: Proud_Infidel  Respond to of 70976
 
AMAT is the arms supplier in this battle:

TSMC, UMC use copper as weapon in marketing battle
By Will Wade
EE Times
(12/03/99, 02:56:29 PM EDT)

SAN JOSE -- Copper processing technology has become the latest card in the high-stakes game for foundry market dominance, as both Taiwan Semiconductor Manufacturing Co. and UMC Group have begun manufacturing chips for customers using the faster metal wiring.

While TSMC remains the market leader, UMC is closing the gap quickly, and claims its technology is more advanced. This is a key element in UMC's plans to make a run for the front position next year.

"TSMC has delivered the foundry industry's first commercially available copper process," said Sheldon Wu, senior director of field technology support for TSMC USA, headquartered in San Jose. The company has several customers now, and is producing chips at the 0.18-micron level, with the top two layers of interconnect wiring using copper.

UMC is also making chips for a single customer at the 0.18-micron level, with two layers of copper. "Those are the most important layers to use copper because that's where the power and clock signals are traveling," said Jim Ballingall, vice president for worldwide marketing at UMC, based in Sunnyvale, Calif. "We're ready to take customer designs now, and have been for a while. We haven't seen significant interest yet, but we expect that we will soon."

Both companies are working to add copper to the rest of the chip and are promising six-layer copper capabilities shortly. UMC will complete pilot qualifications this month, and TSMC will make its process commercially available next quarter. "Our leading-edge customers are starting to use this leading-edge technology," Wu said.

However, the foundry market is not bracing for an onslaught of orders for copper chips, and neither company will have significant capacity for the technology until at least the end of next year.

TSMC plans to ramp its all-copper process by the third quarter of 2000 and should be able to produce about 6,000 8-inch wafers per month. Initially the production will be at the company's Fab 4 in Hsinchu, Taiwan, but will later move to its larger Fab 6, which is just coming online in the southern city of Tainan. UMC has two new facilities in Hsinchu where copper projects are under way, and expects to be able to manufacture up to 10,000 wafers per month by the end of next year.

Although current demand is slim, this is the right time to introduce the process, according to Joanne Itow, foundry analyst for Semico Research Corp. in Phoenix. "I think there will be a demand for copper chips, but it will take time to develop," she said. "Right now it's a way to attract customers, so copper interconnect manufacturing capability is a good thing for a foundry to have in its bag of tricks."

While both firms are on comparable development paths, their plans diverge on pricing. TSMC's Wu said the company would not charge a premium for copper-based chips, while UMC said it will. "Our costs are higher for this process, so we will charge a higher price to offset that," Ballingall said.

In fact, higher pricing in general is part of UMC's current strategy to increase revenue. The company's current prices run about 10% to 15% lower than rival TSMC's, according to John Hsuan, UMC's chief executive officer. "We need to bring our prices higher in order to be more in line with our competition," he said. "We would like our prices to be within 5% of their prices."

The goal of that strategy is nothing less than market dominance. UMC has been increasing its revenues faster than TSMC for several years and is poised to make a run for the top slot. "The trends indicate that we will pass TSMC in revenue sometime next year," Hsuan said. "Right now it's a capacity game, and if we want to pass them, we have to increase our capacity."

UMC's total capacity now is about 1.7 million 8-inch wafers, compared with TSMC's capacity of 1.9 million wafers. Both have ambitious expansion plans in progress, which will allow UMC to boost its capacity next year to 2.4 million wafers. TSMC, for its part, will increase its production to 2.8 million wafers.

Despite lower prices and lower capacity, UMC is clearly catching up to its rival. Between 1995 and 1999, the company's revenue increased at a cumulative rate of 61%, while TSMC's revenue increased by only 16%. Hsuan said that UMC's share of the overall foundry market has increased from 14% in 1997 to 27% today, while TSMC's share has hovered at around 30%. And most significantly, UMC's total revenue figures were about one-quarter the size of TSMC's in 1995, but Hsuan predicts they will reach 88% of their rival's sales this year.

"TSMC has stayed fairly flat for the past few years, while we are growing significantly," he said. "We will catch them very soon."

TSMC chairman Morris Chang doesn't think that will happen. "They are growing, but our strategy is to make the gap between us larger. I don't think it is possible for them to close the gap completely," he said. "I'm going to make sure of that."

Besides capacity, he pointed to service as TSMC's strong suit. According to Chang, price should only rank third as a customer's priority, after service and flexibility in handling orders.

In contrast, UMC said technology is its competitive advantage. "We have better technology. We were the first foundry to ramp an 0.18-micron process," said Chris Chi, senior vice president with UMC and director of Fab 8f, one of the company's new facilities. "This will be the most advanced fab in our company, and at least for now, we think it will be the most advanced fab in Taiwan."

With fabless companies sprouting up every day and major chip companies outsourcing more and more production from their own fabs to the foundries, the business is there for either company to grab. Both report that their fabs have been buzzing at just over 100% capacity for several months, and even with a short time-out for the Sept. 21 earthquake, they have since resumed full production.



To: Proud_Infidel who wrote (33425)12/6/1999 9:35:00 AM
From: Proud_Infidel  Read Replies (1) | Respond to of 70976
 
TSMC aims to jumpstart copper in foundry with 0.18-micron process

Semiconductor Business News
(12/06/99, 08:40:09 AM EDT)
HSINCHU, Taiwan --To convince silicon foundry customers that it's time to start using copper interconnects in new IC designs, Taiwan Semiconductor Manufacturing Co. Ltd. here today launched a 0.18-micron technology and a marketing campaign to create partnerships between TSMC and early adopters of two-layer copper metal processes.

TSMC said its new commercial copper process is ready for volume production following a year of prototype fabrication for several foundry customers. The two-layer copper process will be followed by the introduction of an all-copper layer interconnect process in the first quarter next year, said Sheldon Wu, senior director of field technical support for North America, based in San Jose.

The foundry company said customer designs are well underway for the two-layer copper process, which uses aluminum for the lower four levels of metal interconnects. High volumes of copper ICs are expected to be pouring out of TSMC fabs in the third quarter of 2000. After the all-copper 0.18-micron process is formally introduced early in 2000, TSMC plans to launch an introductory two-layer copper process with 0.15-micron design rules in the second quarter next year.

A 0.13-micron copper process is slated to be available from TSMC in the second quarter of 2001. This technology will most likely be introduced with all layers available in copper since metal lines are shrinking to the point that electromigration becomes a major reliability concern, Wu said.

With today's formal introduction of the two-layer copper 0.18-micron process, TSMC claims to be the first pure-play foundry to offer the metal as a commercial technology. Crosstown rival UMC Group has also announced copper processing capabilities over the past year, and it has also been producing engineering prototypes of ICs with two and three layers of copper interconnect for a number of customers, said Jenkon Chen, senior department manager for logic, technology and process development at UMC in Hsinchu. UMC expects the initial copper IC designs to enter volume production in the middle of 2000, according to Chen.

While the world's two largest silicon foundry companies are racing each other in near-lockstep fashion, TSMC said it now is pushing copper into the mainstream by offering incentives to customers willing to move ahead with the initial two-layer copper process. The 0.18-micron process uses fluorinated silicon glass (FSG) as a low-k dielectric insulator between metal layers to help reduce capacitance, Wu said. The same FSG dielectric material is also being used in TSMC's 0.18-micron all-aluminum process.

The two-layer copper process is being marketed as a technology for sharing "risk" between TSMC and early adopters. "We call this 'risk' production," said Wu, explaining that the concept is to take a conservative step towards copper processes at this stage in the technology.

"This means the new technology has passed the process level of qualification with a TSMC test vehicle, and we have passed some level of device type reliability/qualification," he said. "However, it requires our partner [customer] to verify the long-term reliability requirements with their own real design."

TSMC has developed its two-layer copper process to be fully compatible with design rules for all-aluminum ICs at the 0.18-micron technology node. "This allows our customers to readily switch existing designs from aluminum to copper," Wu explained.

In addition, TSMC said it offering pricing incentives to early copper users, but company officials would not discuss specific prices in the program, except to say that the foundry was not charging a high premium for the metal. In fact, an IC with six-layers of aluminum interconnect could be priced higher than the same design in the two-layer copper process, hinted one TSMC official.

TSMC has partnered with a number of fab equipment suppliers to accelerate the commercial availability of copper processes, Wu said. Applied Materials Inc. in Santa Clara, Calif., has been a chief contributor in TSMC's copper process development since the foundry company set up its R&D in July 1998. (Meanwhile, foundry rival UMC has based its copper processes on tools from Novellus Systems Inc. and its coalition of equipment suppliers, according to company managers.)

The 0.18-micron copper process will be released to production initially in TSMC's 8-inch fabs, located in the Hsinchu Science-Based Industrial Park. Full production is expected to include TSMC's Fab 6, located in Taiwan's new Tainan Science-Based Industrial Park in the southern part of the island.

By the third quarter of 2000, TSMC said it will be able to fabricate 40,000 copper layers per month. This capacity is roughly greater than 6,000 eight-inch wafers a month. In 1999, TSMC had copper-processing capacity installed for a total of about 10,000 wafers, according to Wu.

TSMC declined to discuss which applications will appear with the two-layer copper processes, except to say they will include a broad range of designs for computing, communications, and consumer products. The early adopters are expected to be in high-performance microprocessors, fast SRAMs, and powerful digital signal processors (DSPs), Wu said.