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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: THE WATSONYOUTH who wrote (82033)	12/3/1999 11:38:00 PM
From: niceguy767	Read Replies (2) \| Respond to of 1574212

Hi Watsonyouth: Yes I have stated my position. Don't see any substance in your commentary addressing "any problem" with any of the assumptions that underly the basis of my ASMD bullishness! If you care to attack my rationale, as opposed to the message I bring (which role/reversal I can appreciate is difficult for some...especially those whop have been slurping at the same trough for an extended period), I should be happy to respond. Please don't just take emotional cheap shots...Tell me why you think AMD won't do $5 billion in sales in Y2000 and at the same time tell me what sales youuuuu,in your wisdom, think they will achieve in Y2000. I think Amd WILL DO $5 BILLION IN y2000and consequently, I'm extremely bullish. What revenues are you projecting for AMD in Y2000? Unless you have a number in mind, I think you must agree that you shouldn't be so hasty in calling down those who do, even if 180 degrees to your view of the universe!!!

To: THE WATSONYOUTH who wrote (82033)	12/4/1999 10:10:00 AM
From: Dan3	Respond to of 1574212

What's next? I've been thinking a bit about the little information out so far about the AMD challenge to Itanium. Eschewing VLIW for a rather plebian extension of registers (Hey, I don't know what the hell is wrong with my vocabulary this morning either, I just got up and the coffee hasn't kicked in yet :-) seems destined to be an underachieving device. But the result is a die size little larger than the existing Athlon - and they've made it clear that they intend to put two on each chip, so that all systems would become MPU systems. NT (er, Windows 2000)is a 2 CPU OS out of the box, as are current or near term Linux, Solaris, etc. so MPU support has been under development and refinement for years now. Intel has been working on its VLIW compiler for several years as well, but it may take a while for such knowledge and experience to be transferred to the various software houses. The challenge to the compiler targeting a VLIW CPU is pretty daunting, stalls and flushes can now be caused by parallel instructions as well as serial ones (though Intel has said it has worked hard to minimize such effects). I wonder if some of goals for a VLIW compiler and a multithreading compiler are mutually exclusive so that a good performing VLIW compiler will be a poor performing multithread compiler. Optimization settings can correct some of that, but I would guess that it would be tough to produce a compiler that was ideal for both. If sledgehammer, the AMD 64 bit extended 32 bit CPU is always packaged with 2 die on a chip, it provides for 2 possibilities that may support better performance. The first is that compilers, and programmers targeting such systems will always know that effort exerted in creating multithreaded applications (which take the best advantage of multiprocessor systems), OS components, etc. will be time well spent, since all sledgehammer systems will be at least dual processor. A more intriguing possibility is that there could be some instructions that would synchronize execution from the dual cores, allowing a handful of 128 bit operations that would be efficient in such a configuration. Could we see a limited number of 128 bit instructions when Sledgehammer is released? ================================================== IBM, with its Power4, is putting two central processing units (CPUs) on a single chip and connecting lots of Power4 chips with super-high-speed data pathways. Compaq's Alpha EV8 chip will use a method called "symmetrical multithreading" that doubles performance with only a minor increase in the size of the chip. And HAL Computer Systems, which makes chips for Fujitsu based on Sun's Sparc designs, said some of the methods Intel is pursuing with its IA-64 chips don't provide much performance benefit. news.cnet.com -------------------------------------------------------- In a trend toward chip-level multiprocessing widely seen at this year's forum, both AMD and IBM said they will put two instantiations of their next-generation processor cores on a single die...... By putting two processor cores on the same die, hiking the core frequency beyond a gigahertz and using deeper pipelining, Weber said Sledgehammer will offer performance equal to or better than Itanium's, and protect customers' existing applications by running X86-based code without alteration. AMD said it will add technical floating-point capabilities to Sledgehammer and the X86-64 instruction set. Weber said dual 32-bit and 64-bit support will be possible by "defining a mode in which all instructions act on 64-bit data." eet.com ======================================================= I'd be very interested in anyone's thoughts on these issues, Dan