Who's Right? The Pros and Cons. The Gray Areas, etc....
Date: 12/06 00:00 EST
Waging A 'Fact' Fight
Dec. 05, 1999 (Electronic Buyers News - CMP via COMTEX) -- The battle
over the meaning and significance of performance measures for
next-generation DRAMs in some respects resembles a food fight among
high-school students. The contenders in the high-tech "fact" fight are
high-speed-DRAM makers, industry analysts, and others, including Intel
Corp.
Left to sort through the smoke, noise, and finger-pointing are
systems designers who must pick the best next-generation main-memory
chips beyond today's 100-MHz and emerging 133-MHz SDRAMs.
Battle lines are drawn largely between industry-standard
double-data-rate (DDR) SDRAM and proprietary Direct Rambus DRAM (Direct
RDRAM) chips competing in a total DRAM market that Phoenix-based Semico
Research Corp. estimates will hit $18.8 billion this year, $27.9
billion next year, and $50.8 billion in 2003.
At the heart of this ruckus is a disagreement about which of the two
primary measures of DRAM performance-bandwidth or latency-matters more
in determining system, particularly PC, performance.
Adding fuel to the controversy, as well as the inevitable numbers
games among the DRAM vendors, are multiple latency specifications and
disagreement about the value of current benchmarks in assessing the
performance of tomorrow's processors, core-logic chipsets, and systems
and applications software.
Consider the following excerpt from a white paper prepared by Samsung
Semiconductor Inc.
"DRAM performance is measured with two metrics: bandwidth and
latency. Surprisingly, one type of memory delivers the highest
performance in both areas-the Rambus DRAM."
But then think about this passage from a document written by Bert
McComas, principal analyst at Inquest Market Research, Gilbert, Ariz.:
"Rambus offers extremely high bandwidth, but has slower latency than
even standard SDRAM."
Who's right?
Memory-market trackers see the likelihood of both DDR SDRAM and
Direct RDRAM finding homes among the many products that use DRAM.
Indeed, most vendors are planning to roll out both types, so they can
give their customers what they want.
But as a practical matter, Direct RDRAM, because of its higher-cost
die and package, and its unique controller, will need high-volume
demand, which means winning a good part of the consumer and PC markets
if it is to become an economically viable technology.
Make no mistake about the power of price in determining a DRAM's
success.
"As usual, one of the key factors in determining what DRAM is good
for a given application is cost," said Jeff Mailloux, director of DRAM
marketing at Micron Technology Inc., Boise, Idaho.
Thus, equipment designers must be convinced that Direct RDRAM has a
clear and compelling price-performance advantage over DDR SDRAM.
Most DRAM players agree there is no simple, absolute answer to the
question of how the bandwidth or latency, or any other performance
measure, of these new high-speed DRAMs will translate into system
performance; and, therefore, no way to accurately predict what the
future holds for DDR SDRAM and RDRAM technologies.
Adding up performance
DRAM vendors and analysts also agree on at least one other point. The
simplest and cheapest way to improve a system's memory-related
performance is to have enough DRAM.
"The single most important determinant of memory performance is the
amount of memory," said Bob Fusco, DRAM product market manager at
Hitachi Semiconductor (America) Inc., San Jose.
Without sufficient memory, data must be pulled from a hard disk, a
process that takes milliseconds and far exceeds any DRAM access delays.
"We spend a lot of time talking about how to save two or three clock
periods and often lose sight of the fact that a 10-ms delay at 100 MHz
is 1 million clocks," Fusco said.
But adding DRAM provides a significant improvement only in systems
that are memory-starved. Its return on cost quickly diminishes past a
certain point, beyond which chip-performance measures (bandwidth and
latency) and various systems issues take over.
That's where the fog rolls in, and factors like processor type, core
logic, and application come into play.
Gray areas
"As we move to higher-speed applications for DRAMs, it becomes more
complex for systems designers to really judge the best memory for their
systems," said Cecil Conkle, assistant vice president of DRAM marketing
at Mitsubishi Electronics America Inc., Sunnyvale, Calif. But "they do
need to understand the burst or clock frequency associated with big
chunks of data, as well as the first access time or latency issues
associated with getting it started."
On the surface, that understanding should come easily. Clock
frequencies and associated maximum data rates are well known: 100- and
133-MHz DDR SDRAMs move data at 1.6 and 2.1 Gbytes/s, respectively;
300- and 400-MHz RDRAMs at 1.2 and 1.6 Gbytes/s, respectively.
What's more, overall access latency, a function of the DRAM chip's
memory-core design and fabrication geometry, varies very little among
mainstream devices. What does differ are the memory core's peripheral
circuitry and opinions on the role that bandwidth and latency will play
on forthcoming platforms and applications.
"In terms of performance, latency is a very key parameter," said Hai
Ho, director of technical services and applications engineering at
Hyundai Electronics America, San Jose. "Bandwidth does play a role, but
only in unique applications where you have consecutive hits. But these
are very rare."
Instead, systems tend to mix read and write operations, Ho said. And
while sometimes the needed data can be accessed from one memory row, in
many cases it can't. When that happens, "you have to start the memory
transaction from scratch, and that's where latency is key," Ho said.
Low latency seems not to be one of the RDRAM's strengths.
"The row-access latency of an RDRAM is 57 ns. That compares with 42
ns for a standard PC133 SDRAM," said David Bondurant, vice president of
marketing applications at Enhanced Memory Systems Inc., Colorado
Springs, Colo.
Moreover, column-access time for an RDRAM is 35 ns, compared with 20
ns for an SDRAM. In benchmarks that hammer at DRAM latency, RDRAMs do
poorly compared with DDR SDRAMs.
Benchmark results published in November by Inquest show DDR SDRAMs to
have a 10% to 30% performance advantage over RDRAMs.
To complicate matters further, actual latency depends on whether
successive data accesses are from the same memory page or if another
page must be addressed, and, in the latter case, if that other page is
in the same bank or not. (Typically, a DRAM chip has four banks, each
containing several thousand pages. Direct RDRAMs, however, have 16
banks.)
Here, said Bondurant, the opportunity for some advocates to indulge
in "specsmanship" is tempting. "Latency is not as simple as one timing
parameter; it's several," he said. "And so, gamesmanship goes on over
the mix of hits, misses, row accesses, and accesses to other banks."
Performance benchmarks are supposed to cut through marketing games,
said Avo Kanadjian, senior vice president of memory marketing at
Samsung Semiconductor, San Jose. "Unless you look at how well a memory
architecture performs when handling an application's instructions,
you're not comparing apples to apples."
Pros and cons
While RDRAM stumbles when it comes to programs that are sensitive to
latency, it scores well when the focus is on bandwidth. For example,
bus turnaround time-the delay in switching between read and write
operations-is another performance factor at which RDRAMs excel.
In contrast, SDRAMs must take time to flush an output pipeline before
swapping operations. Thus, when Intel wanted to get the point across
that bandwidth was extremely important, the company created a benchmark
that circumvented the processor's L1 and L2 caches and alternated read
and write operations, Hitachi's Fusco said.
The reason for disabling the cache memories is that, sitting between
the processor and main memory, fast-cache SRAMs can obscure much of a
DRAM's performance characteristics, adding to the difficulty of
comparing memory architectures.
Coping strategy
One way to deal with the confusion of multiple-performance figures
and benchmarks is to assign an effective or sustained bandwidth that
takes into account not only a DRAM's peak bandwidth and random-access
latency, but also systems- and applications-oriented factors like burst
length and bus turnaround time, as well as systems-utilization factors
like applications software and (in the case of PCs) details of the
BIOS.
Systems and applications factors are important, as benchmarks
indicate, because they might stress some performance factors while
masking others. And ultimately, it's the end customer's perceptions of
performance more than any DRAM specifications that matter.
"Most memory suppliers talk about peak bandwidth because it's a
simple calculation, and it's what we know our memory is capable of,"
said Kevin Kilbuck, memory engineering manager at Toshiba America
Electronic Components Inc., Irvine, Calif. "But from the systems side,
chipset and microprocessor designers like to talk about effective
bandwidth because that's what they can actually get from the memory."
The factors considered in calculating effective bandwidth, as Toshiba
defines it, are chip parameters such as latency, number of banks, and
bus turnaround time.
In addition, applications factors are summed up by burst length,
which takes advantage of the DRAM's peak bandwidth. That is, the longer
a burst, the more a DRAM's peak bandwidth weighs in.
These factors are combined to yield a measure of bus use-the
percentage of time that the memory bus is active in writing or reading
data. Finally, effective bandwidth is determined by multiplying bus
utilization and the DRAM's peak bandwidth.
Enhanced Memory's Bondurant describes a similar idea for pegging the
actual system performance attributed to DRAM, called sustained
bandwidth. Using Toshiba's definition for effective bandwidth as a
measure, RDRAMs score well, with a maximum value of 1.19 Gbytes/s (for
a 400-MHz clock), compared with 897 Mbytes/s for 266-MHz DDR SDRAM.
Moreover, RDRAMs are expected to show even better results as new
processors, chipsets, and applications emerge to take advantage of
their very high data bandwidth.
Two sides
Then again, even that argument cuts both ways. "One of the things
affecting latency right now is Intel's P6 and Pentium buses," Hitachi's
Fusco said. As a result of their quirks, "the Intel platform was unable
to take advantage of the lower-latency DRAMs."
That's changing, however. Fusco and others have noted that, in
contrast to Intel's 100- and 133-MHz system bus, the Athlon processor
from AMD Inc. sports a system bus that screams along at 200 MHz and
does a better job of exploiting fast memory.
More specsmanship? Unlikely.
The move to 200 MHz represents "a pretty hefty increase," noted Desi
Rhoden, president and chief executive of San Jose-based Advanced Memory
International Inc., a coordinating body for vendors of JEDEC-standard
memories, which RDRAMs are not.
"Anytime you double something as significant as your system
interface, you'll be able to feel that when you walk up to the
machine," Rhoden said.
-Gil Bassak is a freelance technical writer based in Ossining, N.Y.
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By: Gil Bassak
Copyright 1999 CMP Media Inc.
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