Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Bill Jackson who wrote (82347)	12/8/1999 12:42:00 PM
From: kash johal	Read Replies (2) \| Respond to of 1579022

Bill, Re:"elmer" You will notice that Elmer will IGNORE the facts regarding the Intel data sheets which also vilate the P=IV equation. You will notice that Elmer will IGNORE the facts regarding his own FUD. First he said that folks use a "wave meter" to test power taking 500ms. Then he changed it to a dynamic IDD test calibrated to a known database. Then he denied the need for a database. You will notice that Elmer has claimed to be a test engineer for microprocessor chips. Yet he cannot get beyond P=IV as the equation. As I am sure you know a first order model for a transistor is a resistor and a switch. When the switch is closed the resistor takes Icc max. When the switch is open it takes Zero current. On the one hand he claims that the power consumed is = Max ICC times max VCC. When he MUST know that an average current must be measured dynamically to emulate real world worst case switching. In fact he states this is subsequent posts IN DIRECT VIOLATION of his equation P=IV. He clearly has an AGENDA to post FUD on this. The reason I am POed is he knows better than to keep posting this CRAP about P=Imax x Vmax. regards, Kash

To: Bill Jackson who wrote (82347)	12/8/1999 2:03:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1579022

Re: "Elmer, A DC spec, no clock dependence? " Doesn't the term "Dynamic" suggest something to you? Re: "I would expect them to test them with a short test like that on wafer and mark them all into a number of virtual bins. Of course some will be disposal stuff and some will need to be further tested. " The spec would be selected largely to reduce fallout to a minimum. Probably ~0.1% representing actual process issues that would pose a reliability problem. Virtual bins may be used but the data would probably only be used for process monitoring or possibly adapting test limits to better screen outlying die that exceed a certain sigma that might better be determined on a fab lot by fab lot basis rather than a single bell curve for the generic process (tighter control). It is also possible to store wafer sort information on the die for reference at final test. There is a limit as to the detail I can provide. Re: "It may be that the ones that take higher currents will end up as lower speed units " Other way around Bill. The high current parts run faster, not slower, unless you mean intentionally limited to lower speed so as not to exceed the specs. Not likely. Re: "). It makes sense to give a final test to the finished boards in the cartridge, but how extensive will that test be? a full load test at max speed will take a long time, so they must take some shortcuts as the time needed to exhaustively test parts may well become excessive?" "exhustively" testing parts is not possible in a production environment nor would it significantly improve quality. A quality level above 99.9% can be achieved in a few seconds for most cases and the other cases get into an area that may invoke my NDA so I can't go there. EP If we are boring the thread perhaps we should take this offline.