Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Charles R who wrote (82606)	12/10/1999 1:14:00 PM
From: Petz	Read Replies (1) \| Respond to of 1572416

Comments on overclocked CuMines and downbinning: <A Coppermine 500E 1.60V @ 776MHz> <A Coppermine 650E 1.65V @ 839Mhz> (from an overclocking site) Tell me if I'm wrong about this, but I got the impression that a small sample taken from each wafer of chips is used to determine what the likely maximum operating frequency is for most of the chips on the wafer, call this Fmax. The chips are tested at Fmax. Those that fail may be tested at a lower frequency, but, if they pass, they are not tested at higher frequencies to see if they can be up-binned. This procedure certainly makes sense for the older PIII's and for the AThlon, because the SRAM has to be selected before the chip is packaged in the Slot package. Even for CPU's without external SRAM, following this type of procedure would save testing time. It would also allow for process changes from wafer to wafer to trade off (for example) yield vs. Fmax. If so, the fact that some 500E Coppermines work at 776 MHz may reflect a greater random variation in operating frequency amongst the chips on each wafer, rather than a downbinning of parts. Downbinning, other than avoiding the 133 MHz bus, does not make any sense when the market is screaming for more high speed chips. Petz