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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (82700)	12/12/1999 1:03:00 AM
From: Elmer	Respond to of 1572941

Re: "This couldn't be done with the original PIII's because the L2 cache speed (SRAM) had to be selected before final packaging. " Good point. I don't know the exact flow for PIIIs but it would make sense that the devices are tested in their package and the clock ratio is fuse selected before mounting on the cartridge. That way the speed would be known before marrying them with the SRAM. A second final test would be needed for the cartridge as well. Re: "I thought perhaps that each batch or each wafer might have a target maximum speed determined by sampling, and that no die on that batch would be tested at higher than the target speed. Doing it this way you could save some test time at the expense of underbinning some parts. If the variation in Fmax, within a wafer or between wafers in a batch, is large, then you could wind up underbinning a lot of parts, leading to overclocking stories like we've read about." The added cost of speed binning all die would probably be no more the $.25 per part and the payback would be > $100 per high speed bin part. A good investment by any account. EP