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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (82701)	12/12/1999 12:58:00 AM
From: Saturn V	Read Replies (2) \| Respond to of 1572208

Ref-<Then every review I've read about the Coppermine is in error -- Anand, Tom's, Sharky, Ars Technica, Aces, etc > I got it from the Microprocessor Design Report in the last few months when it covered the Coppermine. I was just as surprised as you are, since a half speed cache appears to be a step backward. (It was the October or November issue, and I could fax it you). The Coppermine uses a 256bit wide path from L2 to L1. Since L2 and L1 are on the same chip, this costs nothing. So a half speed L2 cache was adequate because the L2/L1 bandwidth is still >2x that of the Celeron approach. And it prevents the SRAM speed from becoming a bottleneck. Intel obviously does not want to call attention to what some may perceive as a step backward.