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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Saturn V who wrote (82709)	12/12/1999 2:01:00 AM
From: Elmer	Respond to of 1572371

Re: "I have the Microprocessor report at work, and I will post what it says on Monday." Fine, post it but are you going to believe it over Intel? EP

To: Saturn V who wrote (82709)	12/12/1999 5:34:00 AM
From: Tenchusatsu	Read Replies (2) \| Respond to of 1572371

Saturn's right, Elmer. If I remember correctly, MPR says "Technically, Coppermine's L2 cache is half-speed." This is because the cache transfers a cacheline (32 bytes) every other clock. It's no big deal, though. That back-side bus interface is so wide, an entire cacheline gets transferred in one clock, instead of four clocks on the older BSB interfaces. Perhaps the old BSB interface also had one dead clock in-between cacheline transfers, and this dead clock carried over into the Coppermine cache. Tenchusatsu