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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (82740)	12/13/1999 1:53:00 AM
From: Charles R	Respond to of 1572460

<the data width to the cache and then halving the speed would be an interesting tradeoff, > Not at all! Half speed means basically one additional clock to a n-stage pipeline and the system level performance hit is probably less than 5% (may be well below that). It has been clear for a long time that latency is more important than bandwidth for typical applications. CuMine just showed how overwhelmingly that is true. If one takes a close look at Athlon 2.5 vs 2 L2 divider one will notice similar results.