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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (83698)	12/20/1999 5:11:00 PM
From: Charles R	Read Replies (1) \| Respond to of 1572209

<The only problem now is validation. It's not easy to rearchitect an L2 cache in the limited time frame that AMD has, especially if they decided to implement a victim cache. Cache coherency is never a fun thing to validate. But then again, who said competing against Intel was easy?> This is one of the elements of the risk-reward ratio I mentioned a post or two back. Whatever L2 AMD adds should give them enough marketing advantage to make the whole effort worth it. <Anyway, Spitfire's 64K L2 cache sounds very interesting. I wonder how it will compare to Intel's upcoming Coppermine-128.> Slightly ahead of CuMine-128 and parity with CuMine-256 in integer code?

To: Tenchusatsu who wrote (83698)	12/20/1999 8:06:00 PM
From: Petz	Read Replies (2) \| Respond to of 1572209

Tench, thanks for your spin on the small 64K "L2" in Spitfire. Another reason that Elmer's "salvaging defective Athlons" explanation doesn't hold water, is that it would be very rare for a 256K or 512K L2 to only have 64K salvageable. Finally, whatever AMD has to compete with the CuMine 128K has to have a very low cost of production, because they will probably be selling for $75. BTW, did you read that the key design problem with the K6-3 was insufficient redundant SRAM columns? -- from JC's a couple weeks ago. Petz