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To: Tony Viola who wrote (25613)1/3/2000 6:47:00 PM
From: JC Jaros  Read Replies (1) | Respond to of 64865
 
Well, I don't want to speak outta school Tony, and I know chip architecture is your gig, but my reference was more toward the nature of RISC -v- CISC. twister doesn't understand 'scalability' and that Intel is at a natural disadvantage.

-JCJ



To: Tony Viola who wrote (25613)1/3/2000 6:57:00 PM
From: Charles Tutt  Read Replies (1) | Respond to of 64865
 
It's certainly not clear to me that the compiler technology will exist in time to take full advantage of the architecture, nor is it clear to me that it'll perform well in environments requiring rapid context switching. The bottom line is that EPIC, being new, is unproven.

Personally, I think Sun's proposal for MAJC "multiprocessor on a chip" is a better idea.

sun.com

As long as code is effectively multithreaded, my guess is it should perform well with such a scheme.

JMHO, of course (and I'm not a computer designer, although I do have a degree in that field).



To: Tony Viola who wrote (25613)1/6/2000 9:57:00 AM
From: Thomas C. Kimmel  Respond to of 64865
 
>>> So what about chip architecture? You see something wrong with the EPIC architecture in Itanium?

digital.com

Hi Tony. I saw this item on the AMD thread (where I don't go frequently). Apparently, someone (DEC!) takes a dim(mer) view of the IA-64 architecture. I'd value your comments on it.

-tck