To: Don Green who wrote (36207 ) 1/4/2000 4:23:00 PM From: Don Green Respond to of 93625
O.T.??? Cypress set to sample quad-port SRAM By David Lammers EE Times (01/04/00, 04:10:53 PM EDT) SAN JOSE ( ChipWire)-- Cypress Semiconductor Corp. is readying samples of a quad-port SRAM tuned to the bandwidth needs of emerging communications applications, featuring 9.6 gigabits per second of total bandwidth. The 1-megabit quad-port design will be produced in a 0.25-micron process, and Cypress expects to offer a 4-Mbit part produced in a finer process in 2001. Running at either 100 or 133 MHz, the synchronous quad-port SRAM can read or write data to each port independently to provide simultaneous access to four processors or buses. Geoff Charubin, director of specialty memories for Cypress, said other SRAM suppliers have offered what he called pseudo quad-port SRAMs. "It is possible to use a four- or six-transistor cell to create the illusion of a four-port design, but this is the first time to our knowledge that a company has created a true quad-port design with a 12-T cell,? he said. ?The reason may be that a 12-T cell is normally bigger than a breadbasket, but we have accomplished a design that, in a quarter-micron process, still has a cell size that we believe is competitive." Customers have gotten around the issue somewhat by using dual-port SRAMs in systems with more complex buses, but those solutions require multiple devices and more complex logic than the quad-port device, according to Cypress. The quad-port design will make it easier to create non-blocking architectures for line cards and other apps in which the goal is to switch data through a memory buffer very quickly, the company said. The quad-port design lets up to four processors access the 64-K x 18 memory simultaneously, with each port supporting different frequencies. Though the four-port devices will cut into the market for dual-port SRAMs, it is not a zero-sum gain. Cypress said it will target fast-growing applications that can support a relatively high per-device cost. The company estimates that quad-port SRAMs will account for about one-fifth of all multiport SRAMs by 2004, or about $60 million that year, up from essentially nothing this year. Charubin outlined several apps that can benefit from the quad-port SRAM. In a 2 x 2 non-blocking switch fabric, the ports will support data being written into the memory array by one port, with that data then becoming immediately accessible for a read from any of the other three ports. In data broadcasting, information could be read by all three of the other ports simultaneously, without one port interfering with any of the others. Quad-port SRAMs also will be used in line cards supporting different speeds or protocols. As data switches between cards, the quad-port could direct a data path from one processing card, using ports one or two, to other line cards that might access ports three and four. Multiprocessor systems will also use quad-ports, he said. The chip includes a maskable burst counter that sequentially counts the bits in each block, useful in systems in which multiple processors seek to access a common memory array while still allowing user-defined private memory areas for each processor. "The burst counter needs to be provided with an initial address, but it will automatically increment with each successive clock," Charubin said. "The counter mask allows the user to . . . change the granularity of the counter increment." Sampling starts this quarter with a 100-MHz device, which goes into production in the second quarter, priced at $98 each in 10,000-unit lots. The 133-MHz device will be priced about 33% higher.