SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Kenith Lee who wrote (86035)1/8/2000 10:26:00 PM
From: Bill Jackson  Read Replies (1) | Respond to of 1573001
 
Kenith, That forms a solid mass with no circulation area for coolant. The structure I envision has a path for a coolant fluid between the layers as modern fast CPUs and memory have a hard time with diffusion cooling from a multilayer package. Currently we have one side bonded to the substrate with thermal glue, and the other just cooled radiatively.
The next step would be to have two circuits facing each other with bumps between them and the backs of each bonded to a cooling surface with thermal glue.
Next you could put a power plane in between those facing layers(+ on one side, - on the other, insulation between) and use patterns of vias and conductive bumps to drop power and ground where needed. There could even be signal vias that cross through via bumps.
Next you could add an active layer between them(this would need a coolant fluid) and the complexity could grow from there. Like a multilayer PCB with spaces between the layers using the bumps as vias and the boards material would be active dice.
Just a thought experiment in how can you make an IC built like a parking garage with cooling, power and signals handled.

Bill