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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Bill Jackson who wrote (87887)	1/18/2000 11:31:00 AM
From: Process Boy	Read Replies (1) \| Respond to of 1574762

Bill - <I speculate that when you make a feature like a notch that is .1 at the bottom there will be some that cut to .09 .08 etc as well as a few that are .11 .12 etc. Whatever there will be some process scatter.> Bill, there is most likely comparable poly feature size scatter in any .18 process, stipulating that I am not commenting specifically on your numbers above at all. Who knows? Intel's process scatter may even be better than un-notched poly. However, these things are left to speculation, and otherwise some form of competitive analysis. <In the absence of truth speculation abounds.> I can't help this. I'm going to give this up. I'll leave you free to speculate on the nature of leakage current. PB

To: Bill Jackson who wrote (87887)	1/18/2000 3:30:00 PM
From: Shane Geary	Read Replies (1) \| Respond to of 1574762

Bill: Re" Now if the notch can be made at .1 +/- .00001 this will not be a problem, however I think that +/- .01 is more like it, or even worse....variation across the wafer/die?" The SIA roadmap says that the TARGET variation for poly gate feature size is that 99.7% (3 sigma) of the gates will be within +/-10% of the nominal dimension. For several reasons, this is a meaningless statement, but it indicates the magnitude of the variation seen. Across a chip (and probably across a wafer), an MPU's poly gate variation will be around this magnitude. Thus we expect about +/-0.01um variation on a 0.1um process. My expectation is that Intel's notch process gives worse performance than that, but better than if the gates had to be defined conventionally at that feature size. Intel know what they're doing. "I speculate that when you make a feature like a notch that is .1 at the bottom there will be some that cut to .09 .08 etc as well as a few that are .11 .12 etc. Whatever there will be some process scatter. The thick ones will limit speed and the thin ones will limit voltage by leakage or punchthrough problems." Well put - but this applies to all poly gates no matter how they were defined, and is the typical method of describing the challenges of lithography for the gate layer of MPUs. Huge attention is paid to this in the industry - it has been calculated that for every 0.001um reduction in process variation you make on a high-end MPU process gate level, you get a revenue increase of $7 per chip because you can now push your process that extra nanometer towards the low end of spec. That's a lot of bucks per wafer.