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To: Steve Lee who wrote (97185)1/22/2000 6:51:00 PM
From: Process Boy  Respond to of 186894
 
Steve - <That begs this general question - If a MicroProcessor manufacturer were trying to increase the frequency of their chip with on die L1 cache, Is the MP or the cache the limiting factor that dictates the frequency ceiling for any given process?>

That is a complex question, that I do not feel comfortable answering, since it is slightly outside my area of expertise. I defer to any one else who wishes to address this.

Scumbria, et al, have speculated that the L2 cache implementation on Coppermine might someday limit its overall clock speed. I have some reservations on this argument, i.e., if Intel keeps ramping Coppermine MHz, the question is some what moot.

PB




To: Steve Lee who wrote (97185)1/23/2000 3:20:00 AM
From: Process Boy  Read Replies (1) | Respond to of 186894
 
Steve - Online article about Intel's notched poly gate

This is the article I referred to earlier that I couldn't find. Has a picture.

semiconductor.net

PB