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Technology Stocks : Frank Coluccio Technology Forum - ASAP -- Ignore unavailable to you. Want to Upgrade?

To: ftth who wrote (1038)	1/26/2000 10:52:00 PM
From: Frank A. Coluccio	Read Replies (1) \| Respond to of 1782

Dave, Thread, Perhaps someone can give a hand here. I received the following email this evening from a lurker in a far off land (New England) who asked: (All emphases are mine.) --- "What are your thoughts on the convergence of QoS and DEN (directory enabled networking) initiatives? I am particularly interested in applying application layer controls to bandwidth provisioning at an optical level. I'm aware of multiple initiatives in this area, particularly from companies like Sirocco and Campio, but would like to hear your take on what direction you think the technology is heading towards." --- Would someone care to comment on these issues, while I attempt to learn what it is, exactly, that the above named companies do? Someone? -------- TIA, Frank

To: ftth who wrote (1038)	1/28/2000 7:27:00 PM
From: ftth	Respond to of 1782

Solidum plans 10-Gbit/s reconfigurable processor By Loring Wirbel, EE Times Jan 28, 2000 (8:53 AM) URL: eetimes.com SCOTTS VALLEY, Calif. — Solidum Systems Corp. plans to turn its Pax pattern description language and its reconfigurable classifier processors into a family of classification cluster devices that can scale to support 10-Gbit/second networks using standard CMOS processes. By using memory for pattern recognition only when absolutely necessary, Solidum supports OC-48 and OC-192 Sonet rates more efficiently than the fixed-function search engines and classifiers now in the marketplace, said vice president of marketing Charlie Jenkins. Solidum began life in Ottawa in 1998 as a promoter of the Pax language to allow easy support of communication protocols in FPGAs and other programmable architectures. While the company still highlights the reuse of its classifier designs in larger ASICs or special board-level accelerator products, it is putting greater emphasis on standard silicon implementations of its classification concepts. Last September, Solidum introduced the first standard Gigabit Ethernet core for packet processing, the Pax.core 1000. This year, the focus will be on extending speeds to 2.5 Gbits/s through debut of the Pax.port 1100 chip in midsummer. Then, Solidum will move to OC-192 speeds by developing clustered classification engines that support special 10-Gbit inverse-multiplexing FIFO buffers, implemented in a chip called Pax.port 5120. Solidum's pattern-matching technologies put it in a league of packet-analysis specialists, where only Agere Inc. (Austin, Texas) and NeoCore Inc. (Colorado Springs, Colo.) are exploring similar territories. Jenkins said that Solidum was encouraged when Lucent Technologies Inc. announced the acquisition of Agere on Jan. 20, since a big player justified both the notion of a dedicated development language and a pattern-matching approach to classifying packets. Avoiding junk bits Solidum said that using a programmable state machine to perform pattern matching allows multilayer packet classification to "defy Moore's Law," because bit patterns for matching do not have to scale up with complexity, as they do with CAM- and SRAM-based searches. Because the engine developed by Solidum can use any arbitrary mix of "care" and "don't-care" bits, it can make even more compact use of memory and code space than the newer ternary CAMs. Jenkins said Solidum calls this "classification gain." A developer can control the mix of relevant bits used in searches and avoid "junk" bits, thereby keeping the size of the search engine and associated pattern memory to a minimum. "We can talk of classification clusters a lot easier than the competition, because each engine constitutes only 5,000 to 10,000 gates," Jenkins said. Developers program Pax.cores through the Pax language, a fourth-generation C-like language used to describe packet attributes. Because developers need the experience of optimizing applications using Pax, the company believes it makes more sense to offer network interface cards based on FPGAs before it turns its engines into standard chips, which will come later. In the next few years, Solidum will act at times as a custom licenser of cores and software development kits — primarily for special-purpose accelerator engines and when processor companies or OEMs want to add classifier cores into a larger design. The core of Solidum's business, however, will be in development of standard classification engine devices. For customers nervous about leaping directly into Pax programming, Solidum offers an incremental approach. A standalone classification processor can perform preprocessing packet filtering. The application observes only the desired streams and decodes bits of those streams. At the next stage, Filtering +, developers use the output classification tags, which Solidum appends to packets. These are user-defined methods of assigning queuing, decoding and field replacement for packets. When tags are used, fewer bits need to be processed.